zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 7

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

Control
Pin #
K10
H10
B10
A10
J10
H5
C2
D2
D3
E1
A9
B9
K1
J5
dpll1_mod_sel0
dpll1_mod_sel1
dpll1_hs_en
dpll2_ref
p1_clk0
diff0_en
diff1_en
p1_clk1
diff0_p
diff0_n
diff1_p
diff1_n
Name
fb_clk
rst_b
Type
I/O
O
O
O
O
O
O
I
I
I
I
I
u
u
u
u
Programmable Synthesizer 1 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 1.544 MHz (DS1).
Programmable Synthesizer1 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p1_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 3.088 MHz (2x DS1).
Feedback Clock (LVCMOS). This output is a buffered copy of the feedback
clock for DPLL1. The frequency of this output always equals the frequency of the
selected reference.
DPLL2 Selected Output Reference (LVCMOS). This is a buffered copy of the
output of the reference selector for DPLL2. Switching between input reference
clocks at this output is not hitless.
Differential Output Clock 0 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 155.52 MHz.
Differential Output Clock 1 (LVPECL). This output can be configured to provide
any one of the available SDH clocks. The default frequency for this clock output
is 622.08 MHz clock.
Reset (LVCMOS, Schmitt Trigger). A logic low at this input resets the device. To
ensure proper operation, the device must be reset after power-up. Reset should
be asserted for a minimum of 300 ns.
DPLL1 Hitless Switching Enable (LVCMOS, Schmitt Trigger). A logic high at
this input enables hitless reference switching. A logic low disables hitless
reference switching and re-aligns DPLL1’s output phase to the phase of the
selected reference input. This feature can also be controlled through software
registers. This pin is internally pull up to Vdd.
DPLL1 Mode Select 1:0 (LVCMOS, Schmitt Trigger). During reset, the levels
on these pins determine the default mode of operation for DPLL1 (Automatic,
Normal, Holdover or Freerun). After reset, the mode of operation can be
controlled directly with these pins, or by accessing the dpll1_modesel register
through the serial interface. This pin is internally pull up to Vdd.
Differential Output 0 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 0 driver is enabled. When set low, the differential
driver is tristated reducing power consumption. This pin is internally pull up to
Vdd.
Differential Output 1 Enable (LVCMOS, Schmitt Trigger). When set high, the
differential LVPECL output 1 driver is enabled. When set low, the differential
driver is tristated reducing power consumption.This pin is internally pull up to
Vdd.
Zarlink Semiconductor Inc.
ZL30119
7
Description
Data Sheet