zl30119 Zarlink Semiconductor, zl30119 Datasheet - Page 21

• Manufacturer Part Number: zl30119
• Description: Low Jitter Line Card Synchronizer
• Manufacturer: Zarlink Semiconductor

(Hex)
Addr
3A
3B
3C
3D
3E
36
37
38
39
3F
40
41
42
43
44
45
46
47
48
49
p0_enable
p0_run
p0_freq_0
p0_freq_1
p0_clk0_offset90
p0_clk1_div
p0_clk1_offset90
p0_offset_fine
p0_fp0_freq
p0_fp0_type
p0_fp0_offset_0
p0_fp0_offset_1
p0_fp0_offset_2
p0_fp1_freq
p0_fp1_type
p0_fp1_offset_0
p0_fp1_offset_1
p0_fp1_offset_2
p1_enable
p1_run
Register
Name
Table 5 - Register Map (continued)
Reset
Value
(Hex)
3E
8F
0F
00
01
00
00
00
05
83
00
00
00
05
00
00
00
83
03
11
Zarlink Semiconductor Inc.
P1 Configuration Registers
ZL30119
Control register to enable p0_clk0, p0_clk1,
Control register for the [7:0] bits of the N of
Control register for the p0_clk0 phase position
Control register for the p0_clk1 frequency
Control register for the output/output phase
Control register to select the p0_fp0 frame
Bits [7:0] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
Control register to select p0_fp1 frame pulse
Bits [7:0] of the programmable frame pulse
Bits [21:16] of the programmable frame pulse
p0_fp0, p0_fp1, the P0 synthesizer and select
the source
Control register to generate p0_clk0, p0_clk1,
p0_fp0 and p0_fp1
N*8k clk0
Control register for the [13:8] bits of the N of
N*8k clk0
coarse tuning
selection
Control register for the p0_clk1 phase position
coarse tuning
alignment fine tuning for p0 path
pulse frequency
Control register to select fp0 type
phase offset in multiples of 1/262.14 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.14 MHz
phase offset in multiples of 8 kHz cycles
frequency
Control register to select fp1 type
phase offset in multiples of 1/262.144 MHz
Bits [15:8] of the programmable frame pulse
phase offset in multiples of 1/262.144 MHz
phase offset in multiples of 8 kHz cycles
Control register to enable p1_clk0, p1_clk1, the
P1 synthesizer and select the source
Control register to generate enable/disable
p1_clk0 and p1_clk1
21
Description
Data Sheet
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W