saa569x NXP Semiconductors, saa569x Datasheet - Page 25

• Manufacturer Part Number: saa569x
• Description: Enhanced Tv Microcontrollers With On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
2002 May 06
Timer/counter Control Register (TCON)
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Timer/counter2 Control Register (T2CON)
TF2
EXF2
RCLK0
TCLK0
EXEN2
TR2
C/T2
CP/RL2
14-bit PWM MSB Register (TDACH)
TPWE
TD13 to TD8
14-bit PWM LSB Register (TDACL)
TD7 to TD0
Timer 0 High byte (TH0)
TH07 to TH00
Enhanced TV microcontrollers with
On-Screen Display (OSD)
BITS
Timer 1 overflow flag: Set by hardware on Timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
Timer 1 run control bit: Set/cleared by software to turn Timer/counter on/off.
Timer 0 overflow flag: Set by hardware on Timer/counter overflow. Cleared by
hardware when processor vectors to interrupt routine.
Timer 0 run control bit: Set/cleared by software to turn Timer/counter on/off.
Interrupt 1 edge flag. Both edges generate flag. Set by hardware when external
interrupt edge detected. Cleared by hardware when interrupt processed.
Interrupt 1 type control bit: Set/cleared by software to specify edge/low level
triggered external interrupts.
Interrupt 0 Edge l flag: Set by hardware when external interrupt edge detected.
Cleared by hardware when interrupt processed.
Interrupt 0 type flag: Set/cleared by software to specify falling edge/low level
triggered external interrupts.
Timer 2 overflow flag: Cleared by software. TF2 will not be set when either
baud rate generation mode or clock out mode.
Timer 2 External Flag: Set on a negative transition on T2EX and EXEN2 = 1. In
Auto-reload mode it is toggled on an under or overflow. Cleared by software.
Receive clock 0 flag: When set, causes the UART to use Timer 2 overflow
pulses. RCLK0 = 0 causes Timer 1 overflow pulses to be used.
Transmit clock 0 flag: When set, causes the UART to use Timer 2 overflow
pulses. TCLK0 = 0 causes Timer 1 overflow pulses to be used.
Timer 2 external enable flag: when set, allows a capture or reload to occur,
together with an interrupt, as a result of a negative transition on input T2EX if in
capture mode or Auto-reload mode with DCEN reset. If in Auto-reload mode and
DCEN is set, this bit has no influence. In the other modes, EXF2 is set and an
interrupt is generated on a HIGH-to-LOW transition on T2EX pin. In all modes,
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
START/STOP control bit: a logic 1 starts Timer 2
Counter Timer selection bit: a logic 1 selects the counter for Timer 2
Capture/Reload flag: selection of mode capture or reload
activate this 14-bit PWM (logic 1)
6 MSBs of 14-bit number to be output by the 14-bit PWM
8 LSBs of 14-bit number to be output by the 14-bit PWM
8 MSBs of Timer 0 16-bit counter
25
FUNCTION
SAA567x; SAA569x
Objective specification