saa569x NXP Semiconductors, saa569x Datasheet - Page 61
saa569x
Manufacturer Part Number
saa569x
Description
Enhanced Tv Microcontrollers With On-screen Display Osd
Manufacturer
NXP Semiconductors
Datasheet
1.SAA569X.pdf
(116 pages)
- Current page: 61 of 116
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Philips Semiconductors
22.1.6.5
The Hamming error flags are set if the on-board
8/4 Hamming checker detects that there has been an
uncorrectable (2-bit) error in the associated byte. It is
possible for the page to still be acquired if some of the
page address information contains uncorrectable errors if
that part of the page request was a ‘Don’t Care’. There is
no error flag for the magazine number because an
uncorrectable error in this information prevents the page
being acquired.
The interrupt sequence (C9) bit is automatically dealt with
by the acquisition section, so that rolling headers do not
contain a discontinuity in the page number sequence.
Table 25 The data in row 25 of the basic page memory
2002 May 06
10 to 23
Enhanced TV microcontrollers with
On-Screen Display (OSD)
COL
0
1
2
3
4
5
6
7
8
9
Row 25 data contents
BIT 7
0
0
0
0
0
0
0
0
0
0
BIT 6
0
0
0
0
0
0
0
0
0
0
PBLF
BIT 5
0
0
0
0
0
0
0
0
0
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
Hamming error
FOUND
unused
BIT 4
61
0
The magazine serial bit (C11) indicates whether the
magazine transmission is serial or parallel. This affects
how the acquisition section operates and is dealt with
automatically.
The newsflash (C5), subtitle (C6), suppress header (C7),
inhibit display (C10) and language control (C12 to 14) bits
are dealt with automatically by the display section.
The update bit (C8) has no effect on the hardware. The
remaining 32 bytes of the page header are parity checked
and written into columns 8 to 39 of row 0. Bytes that pass
the parity check have the MSB set to a logic 0 and are
written into page memory. Bytes with parity errors are not
written into the memory.
BIT 3
MU3
PU3
HU3
PT3
C10
C14
C4
C6
0
0
MAG2
SAA567x; SAA569x
BIT 2
MU2
PU2
MT2
HU2
PT2
C13
C5
C9
0
Objective specification
MAG1
BIT 1
MU1
PU1
MT1
HU1
PT1
HT1
C12
C8
0
MAG0
BIT 0
MU0
PU0
MT0
HU0
PT0
HT0
C11
C7
0
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