saa569x NXP Semiconductors, saa569x Datasheet - Page 45

• Manufacturer Part Number: saa569x
• Description: Enhanced Tv Microcontrollers With On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
14.1
The Watchdog Timer operation is activated when bit WLE
in the Power Control SFR (PCON) is set. The Watchdog
can be disabled by software by loading the value 55H into
the Watchdog Timer Key SFR (WDTKEY). This must be
performed before entering Idle/Power-down mode to
prevent exiting the mode prematurely.
Once activated, the Watchdog Timer SFR (WDT) must be
reloaded before the timer overflows. Bit WLE must be set
to enable loading of the WDT SFR. Once loaded, bit WLE
is reset by hardware, to prevent erroneous software from
loading the WDT SFR.
The value loaded into the WDT defines the Watchdog
Interval (WI):
For a 12 MHz microcontroller clock; t = 32.768 ms.
The range of intervals is from WDT = 00H, this gives
8.38 ms to WDT = FFH, which gives 32.768 ms.
15 PORT ALTERNATIVE FUNCTIONS
Ports 1, 2 and 3 are shared with alternative functions to
enable control of external devices and circuits. These
functions are enabled by setting the appropriate SFR and
also writing a logic 1 to the port bit that the function
occupies.
16 PULSE WIDTH MODULATORS
The device has eight 6-bit PWM outputs for analog control
of e.g. volume, balance, bass, treble, brightness, contrast,
hue and saturation. The PWM outputs generate pulse
patterns with a repetition rate of 21.33 s, with the high
time equal to the PWM SFR value multiplied by 0.33 s.
The analog value is determined by the ratio of the high
time to the repetition time. A DC voltage proportional to the
PWM setting is obtained by means of an external
integration network (low-pass filter).
16.1
The relevant PWM is enabled by setting the PWM enable
bit PWxE in the PWMx Control Register. The high time is
defined by the value PWxV<5:0>.
2002 May 06
WI
Enhanced TV microcontrollers with
On-Screen Display (OSD)
=
Watchdog Timer operation
PWM control
256 WDT
–
t
45
16.2
The device has a single 14-bit TPWM that can be used for
Voltage Synthesis Tuning. The method of operation is
similar to the normal PWM, except that the repetition
period is 42.66 s.
16.2.1
Two SFRs are used to control the TPWM: TDACL and
TDACH. The TPWM is enabled by setting bit TPWE in the
TDACH SFR. The most significant bits TD<13:7> alter the
high period between 0 and 42.33 s. The seven least
significant bits TD<6:0> extend certain pulses by a further
0.33 s. For example, if TD<6:0> = 01H, 1 in 128 periods
will be extended by 0.33 s. If TD<6:0> = 02H,
2 in 128 periods will be extended.
The TPWM will not start to output a new value until TDACH
has been written to. Therefore, if the value is to be
changed, TDACL should be written before TDACH.
16.3
Four successive approximation ADCs can be
implemented in software by using the on-board 8-bit
Digital-to-Analog Converter and Analog Comparator.
16.3.1
The control of the required analog input is done using
channel select bits CH<1:0> in the SAD SFR. This selects
the required analog input to be passed to one of the inputs
of the comparator. The second comparator input is
generated by the DAC, whose value is set by bits
SAD<7:0> in the SAD and SADB SFRs. A comparison
between the two inputs is made when the start compare
bit ST in the SAD SFR is set. This must be at least one
instruction cycle after the SAD<7:0> value has been set.
The result of the comparison is given on VHI one
instruction cycle after bit ST is set.
16.3.2
The external analog voltage that is used for comparison
with the internally generated DAC voltage does not have
the same voltage range due to the 5 V tolerance of the pin.
It is limited to V
0.75 V. For further details, refer to the “SAA55XX and
SAA56XX Software Analogue to Digital Converter
Application Note SPG/AN99022” .
Tuning Pulse Width Modulator (TPWM)
Software ADC (SAD)
TPWM
SAD
SAD
CONTROL
INPUT VOLTAGE
DDP
CONTROL
V
tn
SAA567x; SAA569x
where V
tn
Objective specification
is a maximum of