saa569x NXP Semiconductors, saa569x Datasheet - Page 44

• Manufacturer Part Number: saa569x
• Description: Enhanced Tv Microcontrollers With On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
13.2.2
In the Auto-reload mode, Timer 2 can be programmed to
count up/down by clearing/setting bit DCEN in T2MOD.
13.2.3
In the Auto-reload mode and when counting up, registers
RCAP2L/RCAP2H are used to hold a reload value for
TL2/TH2 when Timer 2 rolls over. By setting/clearing
bit EXEN2 in T2CON, external trigger T2EX on Port 3.4
can be enabled/disabled. If EXEN2 = 0, Timer 2 is a 16-bit
timer/counter which, upon overflow, sets TF2 and reloads
TL2/TH2 with the reload value in RCAP2L/RCAP2H.
If EXEN2 = 1, Timer 2 does the above, but with the added
feature that a HIGH-to-LOW transition at the external
trigger T2EX on Port 3.4 causes the current
RCAP2L/RCAP2H value to be loaded into TL2/TH2
respectively, and bit EXF2 in T2CON to be set.
Timer 2 interrupt is set if EXF2 or TF2 is set.
13.2.4
In this mode Timer 2 counts up. When Timer 2 overflows
(FFFFH state), bit TF2 is set. This reloads TL2 and TH2
with the contents of RCAP2L and RCAP2H, respectively.
On overflow, bit EXF2 is inverted and hence toggles
during operation, so that bit EXF2 can be used as 17
if desired.
Timer 2 interrupt will be set only if TF2 is set.
13.2.5
In this mode Timer 2 counts down. Underflow will occur
when the contents of TL2/TH2 match the contents of
RCAP2L/RCAP2H. A Timer 2 roll-over from 0000H to
FFFFH is not considered as an underflow. Upon
underflow, bit TF2 will be set and registers TL2/TH2 will be
loaded with FFFFH. In addition, an underflow will cause
bit EXF2 to be inverted, such that it can be used as the
17
Timer 2 interrupt is set only if TF2 is set.
2002 May 06
Enhanced TV microcontrollers with
On-Screen Display (OSD)
th
bit, if desired.
A
C
C
C
UTO
OUNTING UP
OUNTING UP
OUNTING DOWN
-
RELOAD MODE
(DCEN = 0)
(DCEN = 1
(DCEN = 1
AND
AND
T2EX = 1)
T2EX = 0)
th
bit,
44
13.2.6
In this mode, timer overflow will load TL2 and TH2 with the
contents of T2CAPL and T2CAPH respectively and it will
not set TF2. Bit EXF2 will be set if EXEN2 is set and a
HIGH-to-LOW transition is detected on pin T2EX
(Port 3.4).
When Timer 2 is configured for timer operation, the timer
increments every state. Normally, as a timer, it would
increment every machine cycle.
Timer 2 interrupt is set only if EXF2 is set.
13.2.7
In the clock output mode, external pin T2 is used as a clock
output. A timer overflow causes TL2 and TH2 to be loaded
with T2CAPL and T2CAPH, respectively. An overflow
toggles bit EXF2, which is connected to pin T2. The
frequency of T2 will be half the overflow frequency. Timer
overflow will not set TF2. A HIGH-to-LOW transition on the
external trigger T2EX on Port 3.4 sets EXF2. It is possible
to configure Timer 2 in clock-out mode and baud generator
mode simultaneously.
Timer 2 interrupt is set only if EXF2 is set.
14 WATCHDOG TIMER
The Watchdog Timer is a counter that, once in an overflow
state, forces the microcontroller into a reset condition. The
purpose of the Watchdog Timer is to reset the
microcontroller if it enters an erroneous processor state
(possibly caused by electrical noise or RFI) within a
reasonable period of time. When enabled, the Watchdog
circuit generates a system reset if the user program fails to
reload the Watchdog Timer within a specified length of
time, known as the Watchdog interval.
The Watchdog Timer consists of an 8-bit counter with a
16-bit prescaler. The prescaler is fed with a signal whose
frequency is
8-bit counter is incremented every ‘t’ seconds where:
t
=
6
B
C
------ -
f
1
clk
AUD RATE GENERATION MODE
LOCK OUTPUT MODE
1
6
f
2
clk
16
(2 MHz for 12 MHz 80C51 core). The
=
6 65536
--------------------------
12 MHz
SAA567x; SAA569x
=
Objective specification
32.768 ms