saa569x NXP Semiconductors, saa569x Datasheet - Page 56

• Manufacturer Part Number: saa569x
• Description: Enhanced Tv Microcontrollers With On-screen Display Osd
• Manufacturer: NXP Semiconductors

Philips Semiconductors
22.1.1
The CVBS switch is used to select the required analog
input, depending on the value of TXT8.CVBS1/CVBS0.
22.1.2
The output of the CVBS switch is passed to a
Differential-to-Single-Ended Converter (DIVIS, not shown
in Fig.17), although here it is used in single-ended
configuration with a reference. A full-flash ADC with a
sampling rate of 12 MHz converts the analog output of the
DIVIS to a digital representation.
22.1.3
The MulVIP (used for data and clock recovery) is a Digital
Signal Processor designed to extract the data and recover
the clock from a digitized CVBS signal.
22.1.4
The data standards and clock rates that can be recovered
are shown in Table 23.
Table 23 Data standards and clock rates
22.1.5
The Data Capture timing section uses the synchronisation
information extracted from the CVBS signal to generate
the required horizontal and vertical reference timings.
The timing section automatically recognizes and selects
the appropriate timings for either 625 (50 Hz)
synchronisation or 525 (60 Hz) synchronisation.
A TXT12.VIDEO SIGNAL QUALITY flag is set when the
timing section is locked correctly to the incoming CVBS
signal. When TXT12.VIDEO SIGNAL QUALITY is set,
another flag TXT12.525/625 SYNC can be used to identify
the standard.
22.1.6
The acquisition section extracts the relevant information
from the serial stream of data from the MulVIP and stores
it in memory.
2002 May 06
625 WST
525 WST
VPS
WSS
Closed Caption
Enhanced TV microcontrollers with
On-Screen Display (OSD)
DATA STANDARD
CVBS S
A
M
D
D
A
NALOG
CQUISITION
ATA STANDARDS AND CLOCK RATES
ATA
ULTI
C
-
RATE
APTURE TIMING
-
WITCH
TO
-D
V
IDEO
IGITAL
I
NPUT
C
6.9375 MHz
5.7272 MHz
5.0 MHz
5.0 MHz
500 kHz
ONVERTER
P
ROCESSOR
CLOCK RATE
(M
UL
VIP)
56
22.1.6.1
A page is requested by writing a series of bytes into the
TXT3.PRD<4:0> SFR, which corresponds to the number
of the page required. The bytes written into TXT3 are
stored in a RAM with an auto-incrementing address. The
start address for the RAM is set using the TXT2.SC<2:0>
(to define which part of the page request is being written)
and TXT2.REQ<3:0> (along with TXT2.ACQ BANK) is
used to define which of the 12 page request blocks is
being modified.
If TXT2.REQ<3:0> is greater than 09H, then data being
written to TXT3 is ignored (applies to Bank 0 and 1).
Table 24 shows the contents of the page request RAM.
Up to 12 pages of Teletext can be acquired on the 12 page
device, when TXT1.EXT PKT OFF is set to logic 1, and up
to 10 pages can be acquired when this bit is set to logic 0.
Table 24 The contents of the Page request RAM
If the ‘Do Care’ bit for part of the page number is set to
logic 0, then that part of the page number is ignored when
the Teletext decoder is deciding whether a page being
received off-air should be stored or not. For example, if the
‘Do Care’ bits for the four subcode digits are all set to
logic 0, then every subcode version of the page will be
captured.
COLUMN
START
0
1
2
3
4
5
6
7
Making a page request
Page Units
Page Tens
Hour Tens
Magazine
Do Care
Do Care
Do Care
Do Care
Do Care
Do Care
Do Care
Minutes
Minutes
PRD4
Hours
Units
Units
Tens
X
SAA567x; SAA569x
HOLD MAG2 MAG1 MAG0
PRD3 PRD2 PRD1 PRD0
MU3
HU3
PU3
PT3
X
X
X
MU2
PU2
HU2
MT2
PT2
Objective specification
X
X
MU1
HU1
MT1
PU1
HT1
PT1
E1
MU0
PU0
HU0
MT0
PT0
HT0
E0