w65c22 Western Design Center, Inc., w65c22 Datasheet
w65c22
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... Aug 6, 2009 W65C22 (W65C22N and W65C22S) Versatile Interface Adapter (VIA) Datasheet ...
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... The sale of any WDC product is subject to all WDC Terms and Conditions of Sales and Sales Policies, copies of which are available upon request. Copyright ©1981-2009 by The Western Design Center, Inc. All rights reserved, including the right of reproduction, in whole or in part, in any form. ...
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... INTRODUCTION ...................................................................................................... 7 2. W65C22 FUNCTION DESCRIPTION ...................................................................... 8 2.1 Peripheral Data Ports ................................................................................................................ 8 2.2 Data Transfer - Handshake Control ....................................................................................... 10 2.3 Read Handshake Control. ....................................................................................................... 11 2.4 Write Handshake Control. ....................................................................................................... 12 2.5 Timer 1 Operation .................................................................................................................... 14 2.6 Timer 1 One-Shot Mode .......................................................................................................... 17 2.7 Timer 1 Free-Run Mode ........................................................................................................... 18 2.8 Timer 2 Operation .................................................................................................................... 19 2.9 Timer 2 One-Shot Mode .......................................................................................................... 19 ...
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... TIMING, AC AND DC CHARACTERISTICS ......................................................... 36 4.1 W65C22 Absolute Maximum Ratings .................................................................................... 36 4.2 DC Characteristics TA= -40°C to +85C° ................................................................................. 37 4.3 AC Characteristic TA=-40°C to 4.4 Timing Diagrams ...................................................................................................................... 43 5. CAVEATS .............................................................................................................. 48 5.1 Older Versions ......................................................................................................................... 48 5.2 Shift Clock ................................................................................................................................ 48 5.3 Bus Holding Pins ..................................................................................................................... 48 5.4 Current Limiting ....................................................................................................................... 48 6. HARD CORE MODEL ........................................................................................... 49 ...
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... FIGURE 2-1 READ HANDSHAKE OPERATION (PA ONLY) ................................................................... 11 FIGURE 2-2 WRITE HANDSHAKE (PA AND PB) ..................................................................................... 12 FIGURE 3-1 W65C22 40 PIN PDIP PINOUT ............................................................................................ 28 FIGURE 3-2 W65C22 44 PIN PLCC PINOUT ........................................................................................... 28 FIGURE 3-3 W65C22N AND GTE - G65SC22 CMOS PORT A BUFFER (PA0-PA7, CA2) .................... 31 FIGURE 4-1 READ TIMING ....................................................................................................................... 44 FIGURE 4-2 WRITE TIMING ...................................................................................................................... 44 FIGURE 4-3 READ HANDSHAKE, PULSE MODE (CA2) .......................................................................... 45 FIGURE 4-4 READ HANDSHAKE, HANDSHAKE MODE TIMING (CA2) ...
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... TABLE 2-1 W65C22 MEMORY MAP OF INTERNAL REGISTERS............................................................ 8 TABLE 2-2 ORB, IRB OPERATION FOR REGISTER 0 ($00) .................................................................... 9 TABLE 2-3 ORA, IRA OPERATION FOR REGISTER 1 ($01) .................................................................... 10 TABLE 2-4 DDRB, DDRA OPERATION ($02,$03) ..................................................................................... 10 TABLE 2-5 CA1, CA2, CB1, CB2 CONTROL1 ($0C) ................................................................................ 12 TABLE 2-6 T1 COUNTER FORMAT AND OPERATION1 ($04,$05) ........................................................ 14 TABLE 2-7 T1 LATCH FORMAT AND OPERATION1 ($06,$07) .............................................................. 15 TABLE 2-8 AUXILIARY CONTROL REGISTER FORMAT AND OPERATION ($0B) ...
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... INTRODUCTION The W65C22 (W65C22N and W65C22S) Versatile Interface Adapter (VIA flexible I/O device for use with the 65xx series microprocessor family. The W65C22 includes functions for programmed control of two peripheral ports (Ports A and B). Two program controlled 8-bit bidirectional peripheral I/O ports allow direct interfacing between the microprocessor and selected peripheral units ...
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... W65C22 FUNCTION DESCRIPTION Table 2-1 W65C22 Memory Map of Internal Registers Register RS Coding Number RS3 RS2 RS1 ...
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When reading the Peripheral Port (PA or PB), the contents of the corresponding Input Register (IRA or IRB) is transferred onto the Data Bus. When the input latching feature is disabled, IRA will reflect the logic levels present on the ...
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... Data Transfer - Handshake Control A powerful feature of the W65C22 is its ability to provide absolute control over data transfers between the microprocessor and peripheral devices. This control is accomplished by way of "handshake" lines. PA lines Peripheral A Control 1, 2 (CA1, CA2) handshake data transfers on both Read and Write operations, while PB lines Peripheral B Control 1,2 (CB1, CB2) handshake data on Write operations only ...
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... To accomplish the Read Handshake, the peripheral device generates a Data Ready signal to the W65C22N that indicates valid data is present PB. In most cases, this Data Ready signal will interrupt the microprocessor, which will then read the data and generate a Data Taken signal. Once the peripheral senses the Data Taken signal, new data will be placed on the bus ...
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... The Write Handshake operation is similar to Read Handshaking. For Write Handshaking, however, the W65C22 generates the Data Ready signal and the peripheral device must generate the Data Taken return signal. Note that Write Handshaking may occur on both PA and PB. For a Write Handshake, CA2 or CB2 serve as the Data Ready output and can operate in either the Handshake Mode or the Pulse Mode ...
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Negative Active Edge 1 = Positive Active Edge ...
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Timer 1 Operation Interval Timer 1 (T1) consists of two 8-bit latches and a 16-bit counter. The latches serve to store data which loaded into the counter. Once the counter is loaded under program control, it ...
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Table 2-7 T1 Latch Format and Operation1 ($06,$07 128 WRITE - 8 bits loaded into T1 low order latches. This operation is no different than a write into theT1 Low Order Register. READ ...
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Table 2-8 Auxiliary Control Register Format and Operation ($0B Timer Control T2 Timer Control T1 Timer Control 7 6 Operation 0 0 Timed interrupt each time T1 is loaded 0 1 Continuous interrupts 1 0 Timed ...
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It should be noted that the microprocessor does not write directly into the T1 low order counter. Instead, this half of the counter is loaded automatically from the low order register when the microprocessor writes into the high order register ...
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... Timer 1 Free-Run Mode An important advantage within the W65C22 is the ability of the latches associated with the T1 counter to provide a continuous series of evenly spaced interrupts or a square wave on PB7. It should also be noted that the continuous series of interrupts and square waves are not affected by variations in the microprocessor interrupt response time ...
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Timer 2 Operation Timer 2 (T2) operates in the One-Shot Mode only (as an interval timer pulse counter for counting negative pulses on PB6. A single control bit within ACR5 is used to select between these ...
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Timer 2 Pulse Counting Mode In the Pulse Counting Mode, T2 counts a predetermined number of negative going pulses on PB6. To accomplish this, a count number is loaded into high order T2 counter, which clears IFR5 logic and ...
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Table 2-10 Shift Register and Auxiliary Control Register Control ($0A SR7 SR6 SR5 ...
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Shift In - Counter T2 Control (001) In this mode, the shifting rate is controlled by the low order eight bits of counter T2. Shift pulses are generated on the CB1 line to control shifting in external devices. The ...
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Shift In - External CB1 Clock Control (011) In this mode, CB1 serves as an input to the SR. In this way, an external device can load the SR at its own pace. The SR counter will interrupt the ...
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Shift Out - T2 Control (101) In this mode, the shift rate is controlled by T2 (as in mode 100). However, with each read or write of the SR Counter is reset and eight bits are shifted onto the ...
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... If an Interrupt Flag is a Logic 1, and the corresponding Interrupt Enable bit is a Logic 1, the IRQB will Logic 0. IRQB on the W65C22S is a full output driver that allows both Logic 1 and Logic 0 levels. The W65C22N and older NMOS and CMOS IRQB output is/was open drain pull down only ...
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IFR7 is not a flag. Therefore, IFR7 is not directly cleared by writing a Logic 1 into its bit position. It can be cleared, however, by clearing all the flags within the register disabling all active interrupts as ...
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Table 2-12 Interrupt Enable Register ($0E Set/Clear Timer1 Timer2 Notes bit "0", then each Logic 1 in bits 0-6 disables the corresponding interrupt bit "1", then each ...
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... PIN FUNCTION DESCRIPTION Figure 3-1 W65C22 40 Pin PDIP Pinout Figure 3-2 W65C22 44 Pin PLCC Pinout 28 ...
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... Chip Select (CS1, CS2B) Normally, CS1 and CS2B are connected to the microprocessor address lines. This connection may be direct or through decoding. To access a selected W65C22 register, CS1 must be logic 1 and CS2B must be logic 0. These pins have a bus holding devices on the W65C22S. Table 3-1 Pin Function Table ...
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... IRQB is low. See Figure 3.4 IRQB for the IRQB buffer schematics for both the W65C22N and W65C22S. The IRQB pin on the W65C22S is a standard totem pole output. The W65C22S IRQB signal was meant for logically ORing rather than wire ORing the IRQ’ system. This change was made to improve the low power, high speed characteristics of the part. For systems that have wire ORed IRQB outputs a solution is to place a low voltage diode (< ...
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... line, bidirectional bus used for the transfer of data, control and status information between the W65C22 and a peripheral device. Each PA bus line may be individually programmed as either an input or output under control of DDRA. Data flow direction may be selected on a line by line basis with intermixed input and output lines within the same port ...
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Figure 3-7 Rockwell – R65NC22 CMOS Port A Buffer (PA0-PA7, CA2) Figure 3-8 Rockwell – R6522 NMOS Port A Buffer (PA0-PA7, CA2) 32 ...
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... PA. With respect to PB, the output signal on line PB7 may be controlled by Timer 1 while Timer 2 may be programmed to count pulses on the PB6 line. The W65C22S PB lines represent one CMOS high impedance load with bus holding device in the input mode and will drive two TTL loads in the output mode. ...
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Figure 3-11 Rockwell - R65NC22 (CMOS), R6522 (NMOS) Port B Buffers (PB0-PB7) * Note: The Rockwell Data Book / Data Sheet has these inverters; however the buffers are really like the G65SC22 buffers we think this is a schematic mistake. ...
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... The RWB signal is generated by the microprocessor and is used to control the transfer of data between the W65C22 and the microprocessor. When RWB Logic 1 and the chip is selected, data is transferred from the W65C22 to the microprocessor (Read operation). Conversely, when RWB is at logic 0, data is transferred from the processor to the selected W65C22 register (Write operation) ...
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... TIMING, AC AND DC CHARACTERISTICS 4.1 W65C22 Absolute Maximum Ratings Table 4-1 Absolute Maximum Ratings Rating Supply Voltage Input Voltage Storage Temperature This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. ...
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... Ioh PB0-PB7 Supply Current (With tester loading) (1) Idd Supply Current (CORE) (1) Input Capacitance MHz Cin* Output Capacitance MHz Cout* Table 4-2b W65C22S DC Characteristics Symbol Parameter Supply Voltage VDD Input High Voltage - All inputs Vih Input Low Voltage - All inputs Vil Input Leakage Current, Vin = 0 ...
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... Figure 4-1a W65C22N IDD vs. VDD Figure 4-2a W65C22N F Max vs. VDD 38 ...
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... Figure 4-1b W65C22S IDD vs. VDD Figure 4-2b W65C22S F Max vs. VDD 39 ...
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... AC Characteristic TA=-40°C to Table 4-3a W65C22N AC Characteristics Symbol tCYC Cycle Time Phase tPWH Width High Phase tPWL Width Low tR,F Phase 2 Transition Select, ACR Setup Select, RWB Hold (PHI2 tCAR edge) Data Bus Delay tCDR Data Bus Hold tHR Time Peripheral tPCR Setup Select, ...
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... Table 4-3b W65C22S AC Characteristics 5.0+/-5% Symbol Parameter Min 14 MHz tCYC Cycle Time 70 Phase 2 Pulse tPWH 35 Width High Phase 2 Pulse tPWL 35 Width Low tR,F Phase 2 Transition - Select, RWB ACR 10 Setup Select, RWB Hold (PHI2 rising tCAR 10 edge) Data Bus Delay tCDR - Data Bus Hold tHR ...
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... Pulse Spacing - CB1 Input Pulse tICS CA1, CB1 Set Up Prior to tAL Transition to Arm Latch Peripheral Data Hold after CA1, tPDH CB1 Transition Note: See Figure 4-12 for test load Table 4-4a W65C22N AC Peripheral Interface Timing 5.0+/-5% Units Min Max 14 MHz - 70 Time, Clock Negative ...
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... Transition to Arm Latch Peripheral Data Hold after CA1, tPDH CB1 Transition Note: See Figure 4-12 for test load 4.4 Timing Diagrams Note: Measurement points are at 50% of VDD unless otherwise specified. Table 4-4b W65C22S AC Peripheral Interface Timing 5.0+/-5% 3.3 +/-10% 3.0+/-5% Min Max Min Max Min Max ...
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Figure 4-1 Read Timing Figure 4-2 Write Timing 44 ...
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Figure 4-3 Read Handshake, Pulse Mode (CA2) Figure 4-4 Read Handshake, Handshake Mode Timing (CA2) Figure 4-5 Write Handshake, Pulse Mode Timing (CA2, CB2) 45 ...
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Figure 4-6 Write Handshake, Handshake Mode Timing (CA2, CB2) Figure 4-7 Peripheral Data, Input Latching Timing Figure 4-8 Data Shift Out, Internal or External Shift Clock Timing 46 ...
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Figure 4-9 Data Shift In, Internal or External Shift Clock Timing Figure 4-10 External Shift Clock Timing Figure 4-11 Pulse Count Input Timing Figure 4-12 Test Load (All Dynamic Parameters) 47 ...
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... Older Versions On older versions of the 6522 and 65C22, which are not internally chip selected, random register are read due to register select values. The W65C22 selects only register 15 ($F) internally. This feature has been added for systems which have indeterminate register select values. ...
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... W65C22C and W65C22S Timing The timing of the W65C22C is the same as the W65C22S in that the input buffers are the same and the output transistor drivers are the same as the W65C22S. When applying the W65C22S core, the output delays should be analyzed after adding the output drive transistors and the output load capacitance. ...
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... Ship and store product in conductive shipping tubes or conductive foam plastic. Never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. Handle MOS parts only at conductive work stations. 3. Ground all assembly and repair tools. Example: W65C22N6TPLG-14 The Western Design Center, Inc. 2166 East Brown Road Mesa, Arizona 85213 USA Fax: 480-835-6442 Info@WesternDesignCenter.com www ...