w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 9

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

When reading the Peripheral Port (PA or PB), the contents of the corresponding Input Register (IRA or IRB)
is transferred onto the Data Bus. When the input latching feature is disabled, IRA will reflect the logic levels
present on the PA bus pins. However, with input latching enabled and the selected active transition on
Peripheral A Control 1 (CA1) having occurred, IRA will contain the data present on the PA bus lines at the
time of the transition. In this case, once IRA has been read, it will appear transparent, reflecting the current
state of the PA bus pins until the next CA1 latching transition.
With respect to IRB, it operates similar to IRA except that for those PB bus pins that have been programmed
as outputs, there is a difference. When reading IRA, the logic level on the pins determines whether logic 1
or 0 is read. However, when reading IRB, the logic level stored in ORB is the logic level read. For this
reason, those outputs which have large loading effects may cause the reading of IRA to result in the reading
of a logic 0 when a 1 was actually programmed, and reading logic 1 when a 0 was programmed. However,
when reading IRB, the logic level read will be correct, regardless of loading on the particular pin.
For information on formats and operation of the PA and PB registers, see Tables 2-2, 2-3 & 2-4. Note that
the input latching modes are controlled by the Auxiliary Control Register (See Table 1-8).
DDRB="1" (Output)
Pin Data Direction
DDRB="0" (Input)
DDRB="0" (Input)
PB7
7
(Input latching
(Input latching
Selection
disabled)
enabled)
PB6
6
Table 2-2 ORB, IRB Operation for Register 0 ($00)
effect on pin level, until DDRB
MPU writes onto ORB, but no
PB5
MPU writes Output Level
5
changed.
WRITE
(ORB)
PB4
4
PB3
3
MPU reads IRB bit, which is the level of the
PB2
MPU reads output register bit in ORB. Pin
2
PB pin at the time of the last CB1 active
PB1
MPU reads input level
1
level has no effect.
on PB pin.
transition.
READ
PB0
0
ORB,IRB
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