w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 10

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

A powerful feature of the W65C22 is its ability to provide absolute control over data transfers between the
microprocessor and peripheral devices. This control is accomplished by way of "handshake" lines. PA lines
Peripheral A Control 1, 2 (CA1, CA2) handshake data transfers on both Read and Write operations, while
PB lines Peripheral B Control 1,2 (CB1, CB2) handshake data on Write operations only.
2.2
DDRA="1" (Output)
(Input latching disabled)
DDRA="1" (Output)
(Input latching enabled)
DDRA="0" (Input)
(Input latching disabled)
DDRA="0 (Input)
(Input latching enabled)
PB7/
PA7
7
Data Transfer - Handshake Control
Pin Data Direction
PA7
"0” Associated PB/PA pin is an input (high impedance)
"1” Associated PB/PA pin is an output, whose level is determined by ORB/ORA Bit.
7
Selection
PB6 /
PA6
6
PA6
6
PB5 /
PA5
5
Table 2-3 ORA, IRA Operation for Register 1 ($01)
PA5
Table 2-4 DDRB, DDRA Operation ($02,$03)
5
MPU writes Output Level
(ORA)
MPU writes into ORA, but no
effect on pin level, until DDRA
changed.
PB4 /
PA4
4
PA4
4
WRITE
PB3 /
PA3
3
PA3
3
PB2 /
PA2
2
PA2
2
MPU reads level on PA pin.
MPU reads IRA bit which is the
level of the PA pin at the time of
the last CA1 active transition.
MPU read level on PA pin.
MPU reads IRA bit which is the
level of the PA pin at the time of
the last CA1 active transition.
PB1 /
PA1
PA1
1
1
PB0 /
PA0
PA0
READ
0
0
DDRB,DDRA
ORA,IRA
10