w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 3

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

1.
2.
3.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
INTRODUCTION ...................................................................................................... 7
W65C22 FUNCTION DESCRIPTION ...................................................................... 8
2.12.1
2.12.2
2.12.3
2.12.4
2.13.1
2.13.2
2.13.3
2.13.4
PIN FUNCTION DESCRIPTION ............................................................................ 28
Peripheral Data Ports ................................................................................................................ 8
Data Transfer - Handshake Control ....................................................................................... 10
Read Handshake Control. ....................................................................................................... 11
Write Handshake Control. ....................................................................................................... 12
Timer 1 Operation .................................................................................................................... 14
Timer 1 One-Shot Mode .......................................................................................................... 17
Timer 1 Free-Run Mode ........................................................................................................... 18
Timer 2 Operation .................................................................................................................... 19
Timer 2 One-Shot Mode .......................................................................................................... 19
Timer 2 Pulse Counting Mode ................................................................................................ 20
Shift Register Operation ......................................................................................................... 20
Shift Register Input Modes ..................................................................................................... 21
Shift Register Output Modes .................................................................................................. 23
Interrupt Operation .................................................................................................................. 25
Peripheral Data Port A Control Lines (CA1, CA2) ................................................................ 29
Peripheral Data Port B Control Lines (CB1, CB2) ................................................................ 29
Chip Select (CS1, CS2B) ......................................................................................................... 29
Data Bus (D0-D7) ..................................................................................................................... 30
Interrupt Request (IRQB) ........................................................................................................ 30
Peripheral Data Port A (PA0-PA7) .......................................................................................... 31
Peripheral Data Port B (PB0-PB7) .......................................................................................... 33
Phase 2 Internal Clock (PHI2) ................................................................................................. 35
Reset (RESB) ............................................................................................................................ 35
Register Select (RS0-RS3) ...................................................................................................... 35
RWB (Read/Write) .................................................................................................................... 35
VDD and VSS ............................................................................................................................ 35
Shift Register Disabled (000) ............................................................................................ 21
Shift In - Counter T2 Control (001) .................................................................................... 22
Shift In - PHI2 Clock Control (010) .................................................................................... 22
Shift In - External CB1 Clock Control (011) ...................................................................... 23
Shift Out - Free Running at T2 Rate (100) ........................................................................ 23
Shift Out - T2 Control (101) ............................................................................................... 24
Shift Out - PHI2 Clock Control (110) ................................................................................ 24
Shift Out - External CB1 Clock Control (111) .................................................................. 25
TABLE OF CONTENTS
3