w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 26

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

IFR7 is not a flag. Therefore, IFR7 is not directly cleared by writing a Logic 1 into its bit position. It can be
cleared, however, by clearing all the flags within the register, or by disabling all active interrupts as
presented in the next section.
Each Interrupt Flag within the IFR has a corresponding enable bit in IER. The microprocessor can set or
clear selected bits within the IER. This allows the control of individual interrupts without affecting others. To
set or clear a particular Interrupt Enable bit, the microprocessor must write to the IER address. During this
write operation, if IER7 is Logic 0, each Logic 1 in IER6 thru IER0 will clear the corresponding bit in the IER.
For each Logic 0 in IER6 thru IER0, the corresponding bit in the IER will be unaffected.
Setting selected bits in the IER is accomplished by writing to the same address with IER7 set to a Logic 1.
In this case, each Logic 1 in IER6 through IER0 will set the corresponding bit to a Logic 1. For each Logic 0
the corresponding bit will be unaffected. This method of controlling the bits in the IER allows convenient
user control of interrupts during system operation. The microprocessor can also read the contents of the
IER by placing the proper address on the Register Select and Chip Select inputs with the RWB line high.
IER7 will be read as a Logic 1.
*
If the CA2/CB2 control in the PCR is selected as "independent" interrupt input, then reading or writing
the output register ORA/ORB will not clear the flag bit. Instead, the bit must be cleared by writing into
the IFR, as described previously.
IRQ
7
Timer1
BIT
0
1
2
3
4
5
6
7
6
CA2 active edge
CA1 active edge
Complete 8 shifts
CB2 active edge
CB1 active edge
Time out of T2
Time out of T1
Any enabled interrupt
Timer2
SET BY
5
Table 2-11 Interrupt Flag Register ($0D)
CB1
4
Read or write (ORA*)
Read or write (ORA*)
Read or write Shift Reg.
Read or write ORB*
Read or write ORB
Read T2 low or write T2 high
Read T1C-L low or write T1L-H high
Clear all interrupts
CLEARED BY
CB2
3
Register
Shift
2
CA1
1
CA2
0
IFR
26