w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 23

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

2.13 Shift Register Output Modes
2.12.4 Shift In - External CB1 Clock Control (011)
In this mode, CB1 serves as an input to the SR. In this way, an external device can load the SR at
2.13.1 Shift Out - Free Running at T2 Rate (100)
This mode is similar to mode 101 in which the shifting rate is determined by T2. However, in mode
100 the SR Counter does not stop the shifting operation. Since SR7 is re circulated back into SR0,
the eight bits loaded into the SR will be clocked onto the CB2 line repetitively. In this mode, the SR
Counter is disabled and IRQB is never set. See Figure 2-9.
its own pace. The SR counter will interrupt the microprocessor after each eight bits have been
shifted in. The SR counter does not stop the shifting operation. Its function is simply that of a pulse
counter. Reading or writing the SR resets IFR2 and initializes the counter to count another eight
pulses. Note that data is shifted during the first PHI2 clock cycle following the positive going edge
of the CB1 shift pulse. For this reason, data must be held stable during the first full cycle following
CB1 going high. See Figure 2-8.
Figure 2-8 Shift In - External CB1 Clock Control Timing
Figure 2-9 Shift Out - Free Running T2 Rate Timing
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