w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 20

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

In the Pulse Counting Mode, T2 counts a predetermined number of negative going pulses on PB6. To
accomplish this, a count number is loaded into high order T2 counter, which clears IFR5 logic and starts the
counter to decrement each time a negative pulse is applied to PB6. When the T2 counter reaches a count
of zero, IFR5 is set and the counter continues to decrement with each pulse on PB6. To enable IFR5 for
subsequent countdowns, it is necessary to reload high order T2 counter. The decrement pulse on line PB6
must be Logic 0 during the leading edge of the PHI2 clock. See Figure 2-5.
The Shift Register (SR) performs bidirectional serial data transfers on line CB2. These transfers are
controlled by an internal modulo-8 counter. Shift pulses can be applied to the CB1 line from an external
source, or (with proper mode selection) shift pulses may be generated internally which will appear on the
CB1 line for controlling external devices. Each SR operating mode is controlled by control bits within the
ACR. See Table 2-10 for control bit information. See also Figures 2-6 through 2-12.
2.10 Timer 2 Pulse Counting Mode
2.11 Shift Register Operation
Figure 2-5 Pulse Counting Mode (Timer 2)
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