w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 25

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

There are three basic interrupt operations, including: setting the interrupt flag within IFR, enabling the
interrupt by way of a corresponding bit in the IER, and signaling the microprocessor using IRQB. An
Interrupt Flag can be set by conditions internal to the chip or by inputs to the chip from external sources.
Normally, an Interrupt Flag will remain set until the interrupt is serviced. To determine the source of an
interrupt, the microprocessor must examine each flag in order, from highest to lowest priority. This is
accomplished by reading the contents of the IFR into the microprocessor accumulator, shifting the contents
either left or right and then using conditional branch instructions to detect an active interrupt. Each Interrupt
Flag has a corresponding Interrupt Enable bit in the IER.
microprocessor (set or reset). If an Interrupt Flag is a Logic 1, and the corresponding Interrupt Enable bit is
a Logic 1, the IRQB will go to a Logic 0. IRQB on the W65C22S is a full output driver that allows both Logic
1 and Logic 0 levels. The W65C22N and older NMOS and CMOS IRQB output is/was open drain pull down
only. The W65C22S IRQB should be logically ORed to reduce power and increase speed or wired ORed
with other devices using a diode that is forward biased when IRQB is low.
All Interrupt Flags are contained within a single IFR.
Interrupt Flag is set, thus allowing convenient polling of several devices within a system to determine the
source of the interrupt.
The IFR and IER format and operation is shown in Tables 2-11 and 2-12. The IFR may be read directly by
the microprocessor, and individual flag bits may be cleared by writing a Logic 1 into the appropriate bit of the
IFR. Bit 7 of the IFR indicates the status of the IRQB output. Bit 7 corresponds to the following logic
function:
IRQ = IFR6 ∧ IER6 ∨ IFR5 ∧ IER5 ∨ IFR4 ∧ IER4 ∨ IFR3 ∧ IER3 ∨ IFR2 ∧ IER2 ∨ IFR1 ∧ IER1 ∨ IFR0 ∧
IER0.
Note: ∧ = Logical AND, ∨ = Logical OR.
2.14 Interrupt Operation
2.13.4
In the mode, shifting is controlled by external pulses applied to the CB1 line. The SR Counter sets
IFR2 for each eight pulse count, but does not disable the shifting function.
microprocessor reads or writes the SR, IFR2 is reset and the counter is initialized to begin counting
the next eight pulses on the CB1 line. After eight shift pulses, IFR2 is set. The microprocessor can
then load the SR with the next eight bits of data. See Figure 2-12.
Figure 2-12 Shift Out - External CB1 Clock Control Timing
Shift Out - External CB1 Clock Control (111)
Bit 7 of this register will be Logic 1 whenever an
The enable bits are controlled by the
Each time the
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