w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 29

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

CA1 and CA2 serve as interrupt inputs or handshake outputs for PA. Each line controls an internal Interrupt
Flag with a corresponding Interrupt Enable bit. CA1 also controls the latching of Input Data on PA. CA1
and CA2 are high impedance CMOS inputs with a bus holding device. In the output mode, CA2 will drive
two standard TTL loads.
CB1 and CB2 serve as interrupt inputs or handshake outputs for PB. Like PA, these two control lines
control an internal Interrupt Flag with a corresponding Interrupt Enable bit. These lines also serve as a
serial data port under control of the SR. Each control line represents a CMOS input with a bus holding
device in the input mode and can drive two standard TTL loads in the output mode.
Normally, CS1 and CS2B are connected to the microprocessor address lines. This connection may be
direct or through decoding. To access a selected W65C22 register, CS1 must be logic 1 and CS2B must
be logic 0. These pins have a bus holding devices on the W65C22S.
3.1
3.2
3.3
Peripheral Data Port A Control Lines (CA1, CA2)
Peripheral Data Port B Control Lines (CB1, CB2)
Chip Select (CS1, CS2B)
CA1, CA2
CB1, CB2
CS1, CS2B
D0-D7
IRQB
PA0-PA7
PB0-PB7
PHI2
RESB
RS0-RS3
R/WB
VDD
VSS
Table 3-1 Pin Function Table
Pin
Peripheral A Control Lines
Peripheral B Control Lines
Chip Select
Data Bus
Interrupt Request
Peripheral I/O Port A
Peripheral I/O Port B
Phase 2 Internal Clock
Reset
Register Select
Read/Write
Positive Power Supply
Internal Logic Ground
Description
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