w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 8

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

2. W65C22 FUNCTION DESCRIPTION
Both PA and PB operate in conjunction with a Data Direction Register (DDRA or DDRB). Under program
control, the DDRA and DDRB specify which pins within the port bus are to be designated as inputs or
outputs. Logic 0 in any bit position of the register will cause the corresponding pin to serve as an input;
while a logic 1 will cause the pin to serve as an output.
When a line is programmed as an output, it is controlled by a corresponding bit in the Output Register (ORA
& ORB). A Logic 1 in the ORA or ORB will cause the corresponding output line to go high, while logic 0 will
cause the pin to go low. Under program control, data is written into the ORA or ORB bit positions
corresponding to the output pins which have been programmed as outputs. Should data be written into bit
positions corresponding to pins which have been programmed as input, the output pins will be unaffected.
2.1
Register
Number
C
D
0
1
2
3
4
5
6
7
8
9
A
B
E
F
Peripheral Data Ports
RS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
RS Coding
Table 2-1 W65C22 Memory Map of Internal Registers
RS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
RS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Designation
ORB/IRB
ORA/IRA
ORA/IRA
Register
DDRB
DDRA
T1C-H
T2C-H
T1C-L
T1L-H
T2C-L
T1L-L
ACR
PCR
IFR
IER
SR
Output Register "B"
Output Register "A"
T1 Low-Order
T2 Low-Order
Latches
Latches
Same as Reg 1 except no "Handshake"
Write
Peripheral Control Register
Data Direction Register "B"
Data Direction Register "A"
Auxiliary Control Register
Interrupt Enable Register
T1 High-Order Counter
T2 High-Order Counter
T1 High-Order Latches
T1 Low-Order Latches
Interrupt Flag Register
Shift Register
Description
T1 Low-Order Counter
T2 Low-Order Counter
Input Register "B"
Input Register "A"
Read
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