w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 19

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

Timer 2 (T2) operates in the One-Shot Mode only (as an interval timer), or as a pulse counter for counting
negative pulses on PB6. A single control bit within ACR5 is used to select between these two modes. T2 is
made up of a write only low order T2 latch, a read only low order T2 counter, and a read/write high order T2
counter. This 16-bit counter decrements at a PHI2 clock rate. See Table 2-9.
WRITE -
READ -
WRITE -
READ -
Operation of T2 in the One-Shot Mode is similar to T1. That is, for each load high order T2 counter
operation, Timer 2 sets IFR5 for each countdown to zero. However, after a time out, the T2 counters roll
over to all 1's ($FFFF) and continues to decrement. This two's complement decrement allows the user to
determine how long IFR5 has been set. Since the Interrupt Flag logic is disabled after the initial interrupt set
(zero count), further interrupts cannot be set by a subsequent count to zero. To enable the Interrupt Flag
logic, the microprocessor must reload high order T2 counter. The Interrupt Flag is cleared by either reading
low order T2 counter or by loading high order T2 counter. See Figure 2-3.
2.8
2.9
Timer 2 Operation
32,768
Timer 2 One-Shot Mode
128
7
7
8 bits loaded into T2 high order counter. Also, low order latches are transferred to low order
counter. IFR5 is reset.
8 bits from T2 high order counter transferred to MPU.
8 bits loaded into T2 low order latches.
8 bits from T2 low order counter transferred to MPU. IFR5 is reset.
16,384
64
6
6
Table 2-9 T2 Counter Format and Operation1 ($08,$09)
8,192
32
5
5
4,096
16
4
4
2,048
3
8
3
1,024
2
4
2
512
1
2
1
256
0
1
0
T2L
T2H
19