w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 31

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

3.6
Peripheral Data Port A (PA0-PA7)
PA is an 8 line, bidirectional bus used for the transfer of data, control and status information between the
W65C22 and a peripheral device. Each PA bus line may be individually programmed as either an input or
output under control of DDRA. Data flow direction may be selected on a line by line basis with intermixed
input and output lines within the same port. When logic 0 is written to any bit position of DDRA, the
corresponding line will be programmed as an input. Likewise, when logic 1 is written into any bit position of
the register, the corresponding data pin will serve as an output. The data read is determined by ORA when
input data is latched into the IRA under control of the CA1 line. All modes are program controlled by way of
the W65C22's internal control registers. Each PA line represents a CMOS capacitive load in the input mode
and will drive two standard TTL loads in the output mode.
The PA data port of the W65C22S has improved high impedance CMOS inputs, bus holding devices and
high speed CMOS output drive for logic 1 level. This allows for higher speed operation no longer dependent
on the RC time constant of older NMOS and CMOS designs. See Figures 3-5 through 3-8 for buffer
schematic comparisons with W65C22N, W65C22S and legacy obsolete versions.
Figure 3-5 W65C22S Port A Buffer (PA0-PA7, CA2)
Figure 3-3 W65C22N and GTE - G65SC22 CMOS Port A Buffer (PA0-PA7, CA2)
31