w65c22 Western Design Center, Inc., w65c22 Datasheet - Page 14

• Manufacturer Part Number: w65c22
• Description: W65c22n And W65c22s Versatile Interface Adapter Via Datasheet
• Manufacturer: Western Design Center, Inc.

Interval Timer 1 (T1) consists of two 8-bit latches and a 16-bit counter. The latches serve to store data
which is to be loaded into the counter. Once the counter is loaded under program control, it decrements at
Phase 2 clock rate. Upon reaching zero, bit 6 of the Interrupt Flag Register (IFR) is set, causing Interrupt
Request ([) to go to Logic 0 if the corresponding bit in the Interrupt Enable Register (IER) is set. Once the
Timer reaches a count of zero, it will either disable any further interrupts (provided it has been programmed
to do so), or it will automatically transfer the contents of the latches into the counter and proceed to
decrement again. The counter may also be programmed to invert the output signal on PB7 each time it
reaches a count of zero. Each of these counter modes is presented below. The T1 counter format and
operation is shown in Table 2-6, with corresponding latch format and operation in Table 2-7. Additional
control bits are provided in the Auxiliary Control Register (ACR) bits 6 and 7 to allow selection of T1
operating modes. The four available modes are shown in Table 2-8.
2.5
Timer 1 Operation
WRITE -
READ -
WRITE -
READ -
32,768
128
7
7
16,384
64
6
6
8 bits loaded into T1 low order latches. Latch contents are transferred into low
order counter at the time the high order counter is loaded.
8 bits from T1 low order counter transferred to MPU. T1 interrupt flag IFR6 is reset.
8 bits loaded into T1 high order latches. Also, both high and low order latches
are transferred into T1 counter and this initiates countdown. T1 interrupt flag
IFR6 is reset.
8 bits from T1 high order counter transferred to MPU.
Table 2-6 T1 Counter Format and Operation1 ($04,$05)
8,192
32
5
5
4,096
16
4
4
2,048
3
8
3
1,024
2
4
2
512
1
2
1
256
0
0
1
T1H
T1L
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