MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 118

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Low-Power Modes (MODES)
11.3.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit from stop mode and sets the
SBSW bit in the break status register. The STOP instruction does not affect break module register states.
11.4 Central Processor Unit (CPU)
11.4.1 Wait Mode
The WAIT instruction:
11.4.2 Stop Mode
The STOP instruction:
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
11.5 Internal Clock Generator Module (ICG)
11.5.1 Wait Mode
The internal clock generator (ICG) module remains active in wait mode. If enabled, the ICG interrupt to
the CPU can bring the MCU out of wait mode.
In some applications, low power-consumption is desired in wait mode and a high-frequency clock is not
needed. In these applications, reduce power consumption by either selecting a low-frequency external
clock and turn the internal clock generator off or reduce the bus frequency by minimizing the ICG multiplier
factor (N) before executing the WAIT instruction.
11.5.2 Stop Mode
The value of the oscillator enable in stop (OSCENINSTOP) bit in the CONFIG2 register determines the
behavior of the ICG in stop mode. If OSCENINSTOP is low, the ICG is disabled in stop and, upon
execution of the STOP instruction, all ICG activity will cease and the output clocks (CGMXCLK,
CGMOUT, COPCLK, and TBMCLK) will be held low. Power consumption will be minimal.
If OSCENINSTOP is high, the ICG is enabled in stop and activity will continue. This is useful if the
timebase module (TBM) is required to bring the MCU out of stop mode. ICG interrupts will not bring the
MCU out of stop mode in this case.
During stop mode, if OSCENINSTOP is low, several functions in the ICG are affected. The stable bits
(ECGS and ICGS) are cleared, which will enable the external clock stabilization divider upon recovery.
The clock monitor is disabled (CMON = 0) which will also clear the clock monitor interrupt enable (CMIE)
and clock monitor flag (CMF) bits. The CS, ICGON, ECGON, N, TRIM, DDIV, and DSTG bits are
unaffected.
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Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from
wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After
exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set.
Disables the CPU clock
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor