MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 94

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Internal Clock Generator (ICG) Module)
clock period tolerance plus 10 percent) must be added. This adjustment can be reduced with trimming.
Table 7-3
7.4.7 Trimming Frequency on the Internal Clock Generator
The unadjusted frequency of the low-frequency base clock (IBASE), when the comparators in the
frequency comparator indicate zero error, will vary as much as ±25 percent due to process, temperature,
and voltage dependencies. These dependencies are in the voltage and current references, the offset of
the comparators, and the internal capacitor.
The method of changing the unadjusted operating point is by changing the size of the capacitor. This
capacitor is designed with 639 equally sized units. Of that number, 384 of these units are always
connected. The remaining 255 units are put in by adjusting the ICG trim factor (TRIM). The default value
for TRIM is $80, or 128 units, making the default capacitor size 512. Each unit added or removed will
adjust the output frequency by about ±0.195 percent of the unadjusted frequency (adding to TRIM will
decrease frequency). Therefore, the frequency of IBASE can be changed to ±25 percent of its unadjusted
value, which is enough to cancel the process variability mentioned before.
The best way to trim the internal clock is to use the timer to measure the width of an input pulse on an
input capture pin (this pulse must be supplied by the application and should be as long or wide as
possible). Considering the prescale value of the timer and the theoretical (zero error) frequency of the bus
(307.2 kHz *N/4), the error can be calculated. This error, expressed as a percentage, can be divided by
0.195 percent and the resultant factor added or subtracted from TRIM. This process should be repeated
to eliminate any residual error.
7.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby modes.
7.5.1 Wait Mode
The ICG remains active in wait mode. If enabled, the ICG interrupt to the CPU can bring the MCU out of
wait mode.
In some applications, low power-consumption is desired in wait mode and a high-frequency clock is not
needed. In these applications, reduce power consumption by either selecting a low-frequency external
clock and turn the internal clock generator off or reduce the bus frequency by minimizing the ICG multiplier
factor (N) before executing the WAIT instruction.
94
shows some typical values for settling time.
1/ (307.2 kHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
1/ (25.8 MHz)
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
τ
1
Table 7-3. Typical Settling Time Examples
1/ (307.2 kHz)
1/ (25.8 MHz)
1/ (6.45 MHz)
1/ (25.8 MHz)
τ
2
84
21
84
N
1
11.9 ms
430 μs
107 μs
141 μs
τ
15
12.0 ms
535 μs
212 μs
246 μs
τ
5
12.3 ms
850 μs
525 μs
560 μs
Freescale Semiconductor
τ
tot