MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 145

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

13.3.2.8 Serial Communications Interface (SCI)
SCI CPU interrupt sources:
13.3.2.9 KBD0–KBD7 Pins
A logic 0 on a keyboard interrupt pin latches an external interrupt request.
13.3.2.10 Analog-to-Digital Converter (ADC)
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
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Mode fault bit (MODF) — The MODF bit is set in a slave SPI if the SS pin goes high during a
transmission with the mode fault enable bit (MODFEN) set. In a master SPI, the MODF bit is set if
the SS pin goes low at any time with the MODFEN bit set. The error interrupt enable bit, ERRIE,
enables MODF CPU interrupt requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.
Overflow bit (OVRF) — The OVRF bit is set if software does not read the byte in the receive data
register before the next full byte enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in the SPI status and control
register.
SCI transmitter empty bit (SCTE) — SCTE is set when the SCI data register transfers a character
to the transmit shift register. The SCI transmit interrupt enable bit, SCTIE, enables transmitter CPU
interrupt requests. SCTE is in SCI status register 1. SCTIE is in SCI control register 2.
Transmission complete bit (TC) — TC is set when the transmit shift register and the SCI data
register are empty and no break or idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt requests. TC is in SCI status
register 1. TCIE is in SCI control register 2.
SCI receiver full bit (SCRF) — SCRF is set when the receive shift register transfers a character to
the SCI data register. The SCI receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI control register 2.
Idle input bit (IDLE) — IDLE is set when 10 or 11 consecutive 1s shift in from the RxD pin. The idle
line interrupt enable bit, ILIE, enables IDLE CPU interrupt requests. IDLE is in SCI status register 1.
ILIE is in SCI control register 2.
Receiver overrun bit (OR) — OR is set when the receive shift register shifts in a new character
before the previous character was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt requests. OR is in SCI status register 1.
ORIE is in SCI control register 3.
Noise flag (NF) — NF is set when the SCI detects noise on incoming data or break characters,
including start, data, and stop bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status register 1. NEIE is in SCI control
register 3.
Framing error bit (FE) — FE is set when a 0 occurs where the receiver expects a stop bit. The
framing error interrupt enable bit, FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
Parity error bit (PE) — PE is set when the SCI detects a parity error in incoming data. The parity
error interrupt enable bit, PEIE, enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Interrupts
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