MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 219

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MC68HC908GT16_07

Manufacturer Part Number
MC68HC908GT16_07
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
TBR2:TBR0 — Timebase Rate Selection
TACK — Timebase ACKnowledge
TBIE — Timebase Interrupt Enabled
TBON — Timebase Enabled
17.5 Interrupts
The timebase module can interrupt the CPU on a regular basis with a rate defined by TBR2:TBR0. When
the timebase counter chain rolls over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt request.
Interrupts must be acknowledged by writing a 1 to the TACK bit.
Freescale Semiconductor
These read/write bits are used to select the rate of timebase interrupts as shown in
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
This read/write bit enables the timebase interrupt when the TBIF bit becomes set. Reset clears the
TBIE bit.
This read/write bit enables the timebase. Timebase may be turned off to reduce power consumption
when its function is not necessary. The counter can be initialized by clearing and then setting this bit.
Reset clears the TBON bit.
1 = Clear timebase interrupt flag
0 = No effect
1 = Timebase interrupt enabled
0 = Timebase interrupt disabled
1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s
Do not change TBR2:TBR0 bits while the timebase is enabled (TBON = 1).
TBR2
0
0
0
0
1
1
1
1
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
Table 17-1. Timebase Rate Selection for OSC1 = 32.768 kHz
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32768
NOTE
8192
2048
128
64
32
16
8
Timebase Interrupt Rate
1024
2048
4096
256
512
Hz
16
1
4
~0.24
1000
~ 3.9
62.5
~0.5
250
ms
~2
~1
Table
17-1.
Interrupts
219

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