MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 96

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Internal Clock Generator (ICG) Module)
7.6.3 Slow External Clock (EXTSLOW)
Slow external clock (EXTSLOW), when set, will decrease the drive strength of the oscillator amplifier,
enabling low-frequency crystal operation (30 kHz–100 kHz) if properly enabled with the external clock
enable (EXTCLKEN) and external crystal enable (EXTXTALEN) bits. When clear, EXTSLOW enables
high-frequency crystal operation (1 MHz to 8 MHz).
EXTSLOW, when set, also configures the clock monitor to expect an external clock source that is slower
than the low-frequency base clock (60 Hz to 307.2 kHz). When EXTSLOW is clear, the clock monitor will
expect an external clock faster than the low-frequency base clock (307.2 kHz to 32 MHz).
The default state for this option is clear.
7.6.4 Oscillator Enable In Stop (OSCENINSTOP)
Oscillator enable in stop (OSCENINSTOP), when set, will enable the ICG to continue to generate clocks
(either CGMXCLK, CGMOUT, COPCLK, or TBMCLK) in stop mode. This function is used to keep the
timebase and COP running while the rest of the microcontroller stops. The clock monitor and
autoswitching functions remain operative.
When OSCENINSTOP is clear, all clock generation will cease and CGMXCLK, CGMOUT, COPCLK, and
TBMCLK will be forced low during stop mode. The clock monitor and autoswitching functions become
inoperative.
The default state for this option is clear.
7.7 Input/Output (I/O) Registers
The ICG contains five registers, summarized in
Several of the bits in these registers have interaction where the state of one bit may force another bit to
a particular state or prevent another bit from being set or cleared. A summary of this interaction is shown
in
96
1. See
$0036
$0037
Addr.
Table
1. ICG control register (ICGCR)
2. ICG multiplier register (ICGMR)
3. ICG trim register (ICGTR)
4. ICG DCO divider control register (ICGDVR)
5. ICG DCO stage control register (ICGDSR)
7.7.1 ICG Control Register
7-4.
Register Name
ICG Multiply Register
ICG Control Register
See page 98.
See page 99.
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
(ICGMR)
(ICGCR)
for method of clearing the CMF bit.
Figure 7-11. ICG Module I/O Register Summary
Reset:
Reset:
Read:
Read:
Write:
Write:
CMIE
Bit 7
0
0
= Unimplemented
CMF
0
N6
6
0
0
(1)
Figure
CMON
N5
5
0
0
7-11. These registers are:
CS
N4
R
4
0
1
= Reserved
ICGON
N3
3
1
0
ICGS
N2
2
0
1
Freescale Semiconductor
U = Unaffected
ECGON
N1
1
0
0
ECGS
Bit 0
N0
0
1