MC68HC908GT16_07 FREESCALE [Freescale Semiconductor, Inc], MC68HC908GT16_07 Datasheet - Page 133

• Manufacturer Part Number: MC68HC908GT16_07
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

SS — Slave Select
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a
1 to a DDRD bit enables the output buffer for the corresponding port D pin; a 0 disables the output buffer.
DDRD7–DDRD0 — Data Direction Register D Bits
Figure 12-15
Freescale Semiconductor
Data direction register D (DDRD) does not affect the data direction of port D pins that are being used
by the SPI module. However, the DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit is clear, or when the
SPI master bit, SPMSTR, is set, the PTD0/SS pin is available for general-purpose I/O. When the SPI
is enabled, the DDRB0 bit in data direction register B (DDRB) has no effect on the PTD0/SS pin.
These read/write bits control port D data direction. Reset clears DDRD7–DDRD0, configuring all port D
pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic.
Address:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Reset:
Read:
Write:
MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
DDRD7
$0007
Bit 7
0
Figure 12-14. Data Direction Register D (DDRD)
DDRD6
6
0
RESET
Figure 12-15. Port D I/O Circuit
DDRD5
5
0
NOTE
DDRD4
DDRDx
PTDx
4
0
Table
DDRD3
12-5.
3
0
DDRD2
2
0
PTDPUEx
DDRD1
1
0
V
DD
30 k
DDRD0
Bit 0
PTDx
0
Port D
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