PEF2091 Siemens Semiconductor Group, PEF2091 Datasheet - Page 219

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PEF2091

Manufacturer Part Number
PEF2091
Description
ICs for Communications(ISDN Echocancellation Circuit)
Manufacturer
Siemens Semiconductor Group
Datasheet

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ST
0
5.2.11
Additional Features Register (ADF).
Reset value: 14
WTC2, WTC1
PCL1, PCL0
UVD
BCL
CBAC
Semiconductor Group
WTC2 WTC1
ADF-Register
Write
7
H
Watchdog Controller
The bit patterns "10" and "01" has to be written in WTC1 and WTC2 by
the enabled watchdog timer within 132ms. If it fails to do so, a reset
signal of 5ms at pin RST is generated
Prescaler
The clock frequency on MCLK is selected by setting the bits according
to the table below:
Undervoltage Detector
1=
0=
Bit Clock
1=
0=
Control BAC
Operates in combination with SWST:SGL and SWST:BS bits to
control the S/G bit and the BAC bit. For the operational description see
"S/G Bit and BAC Bit Operations", page 198
6
PCL1
Enables the undervoltage detector. For details see
"Undervoltage Detection", page 92
Disables the undervoltage detector
Changes the DCL-output into the bit-clock mode
Gives the doubled bit clock on the DCL-output
PCL1
Address E
5
0
0
I
I
PCL0
4
H
219
PCL0
3
1
0
0
I
I
UVD
2
Frequency at
MCLK (MHz)
BCL
1
Register Description
7.68
3.84
1.92
0.96
CBAC
Data Sheet 01.99
0
PEB 2091
PEF 2091

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