PEF2091 Siemens Semiconductor Group, PEF2091 Datasheet - Page 95

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PEF2091

Manufacturer Part Number
PEF2091
Description
ICs for Communications(ISDN Echocancellation Circuit)
Manufacturer
Siemens Semiconductor Group
Datasheet

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PEB 2091
PEF 2091
Functional Description
The clock MCLK is delivered during reset (except for power-on and undervoltage
detection).
Table 13 shows that the output pin RST is controlled by power-on reset, undervoltage
detection and the watchdog timer. Figure 38 illustrates the reset sources that have an
impact on pin RST.
Undervoltage
67 ms
Detection
60-70 ms
+
RST
Power-On Reset
5 ms
Watchdog
Figure 38
Reset Sources
3.16
Test Block
In stand-alone mode the two pins TP and TP1 are used for internal manufacturing device
tests. In microprocessor mode only pin TP is used for device test. Test pins are not
defined for normal system operation, as described in this document, and should
therefore be left unconnected.
Semiconductor Group
95
Data Sheet 01.99

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