PEF2091 Siemens Semiconductor Group, PEF2091 Datasheet - Page 54

• Manufacturer Part Number: PEF2091
• Description: ICs for Communications(ISDN Echocancellation Circuit)
• Manufacturer: Siemens Semiconductor Group

Semiconductor Group
Table 6
Mode
Normal
(Tristate)
Normal
(Open Drain
1) See also "ADF2-Register", page 214
2) Refer to Notes 10, page 72, 12, page 72, and 15, page 73 for explanation about active and passive
3) In TE mode bit number 27 of channel 2 (S/G bit) may be driven if the ’S/G bit control’ function is
4) External pull-up resistors required (typ.1 k )
Applications in which the IEC-Q is not the only potential IOM
board have to deal with IOM
applications are dual mode S- or U-terminals and circuits (see "Dual Mode U and S
Terminals and PC Cards", page 27). Typical applications would include the ISAC
(PSB 2186) or the IPAC (PSB 2115) in TE mode. Both devices output FSC and DCL
during and after reset.
The PEB/F 2091 V5.3 in the 64 pin packages (T-QFP-64 or M-QFP-64) has a pin (pin
64, ICE) which allows to enable or disable the IOM
possible to change the status of pin ICE without the need of a reset signal being applied.
In µP mode the status of pin ICE can be overridden by bit ADF2:ICEC. Basically, the
value of pin ICE and the bit-value are EXORed (see Table 7 below).
This function can also be controlled in the P-LCC-44 package in the microprocessor
mode (PMODE = "1") by bit ADF2:ICEC, see "ADF2-Register", page 214.
The following table gives an overview of the control mechanisms of this function in
different settings. The terms "Idle" and "active" of the IOM
defined as follows:
Idle means that no FSC and DCL clocks are output. Clocks may be applied to pins FSC
and DCL. However, they are ignored by the IEC-Q. Data on pin DIN is ignored. Internally,
the DIN signal will be clamped to ’1’. Pin DOUT is ’floating’, which is the same behavior
as described in "DOUT Driver Modes", page 53.
channels
being used (see "S/G Bit and BAC Bit Operations", page 198)
IEC-Q. See Table 2, page 51. For a detailed description of the IOM
interface refer to section 3.6, page 70.
4)
Setting DOUT Driver in µP Mode
)
Pin
RES
1
1
Bit
ADF2:
DOD
0
1
®
-2 clock conflicts during and after reset. Among these
1)
Pin DOUT Output Driver
Value
0
1
0
1
54
DOUT in
active IOM
Channel
low
high
low
floating
®
-2 clocks and the data-lines. It is
2)
®
®
-2
-2 interface in Table 7 are
Functional Description
®
DOUT in
passive
IOM
Channel
high Z
floating
-2 clock master on the
®
-2
3)
Data Sheet 01.99
PEB 2091
PEF 2091
®
-S TE
®
-2