PEF2091 Siemens Semiconductor Group, PEF2091 Datasheet - Page 84

• Manufacturer Part Number: PEF2091
• Description: ICs for Communications(ISDN Echocancellation Circuit)
• Manufacturer: Siemens Semiconductor Group

Semiconductor Group
3.7.1
Figure 32
The LT mode is typically chosen for ISDN-line card applications. The U transceiver has
to synchronize onto an externally provided PTT-master clock. A phase locked loop (PLL)
is required to generate the IOM
(Data Clock) as well as the 15.36 MHz IEC-Q master clock.
XIN/XOUT
Pin XOUT should be left open.
The synchronized 15.36 MHz clock should be provided on pin XIN. A synchronized
IEC-Q system clock guarantees that U-interface transmission will be synchronous to the
PTT-master clock.
Interface
Interface
Interface
U
U
U
LT Mode
Clock Generation for LT Mode
(
Downstream
Synchr.
LT
LT
LT
1
8
2
)
FSC
DCL
XIN
FSC
DCL
XIN
FSC
DCL
XIN
®
-2 clock signals FSC (Frame Synchronization) and DCL
512-4096 kHz
84
15.36 MHz
8 kHz
PLL
%
Functional Description
PTT Ref. Clock
Data Sheet 01.99
PEB 2091
PEF 2091