S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 1034

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S9S12GN16F0VLF

Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12GN16F0VLF

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
The Flash memory may be read as bytes and aligned words. Read access time is one bus cycle for bytes
and aligned words. For misaligned words access, the CPU has to perform twice the byte read access
command. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on EEPROM memory. It
is not possible to read from EEPROM memory while a command is executing on P-Flash memory.
Simultaneous P-Flash and EEPROM operations are discussed in
Both P-Flash and EEPROM memories are implemented with Error Correction Codes (ECC) that can
resolve single bit faults and detect double bit faults. For P-Flash memory, the ECC implementation
requires that programming be done on an aligned 8 byte basis (a Flash phrase). Since P-Flash memory is
always read by half-phrase, only one single bit fault in an aligned 4 byte half-phrase containing the byte
or word accessed will be corrected.
29.1.1
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including
program and erase) on the Flash memory.
EEPROM Memory — The EEPROM memory constitutes the nonvolatile memory store for data.
EEPROM Sector — The EEPROM sector is the smallest portion of the EEPROM memory that can be
erased. The EEPROM sector consists of 4 bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters
required for Flash command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two
sets of aligned double words with each set including 7 ECC bits for single bit fault correction and double
bit fault detection within each double word.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased.
Each P-Flash sector contains 512 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Version
ID, and the Program Once field.
29.1.2
29.1.2.1
Freescale Semiconductor
128 Kbytes of P-Flash memory composed of one 128 Kbyte Flash block divided into 256 sectors
of 512 bytes
Glossary
Features
P-Flash Features
MC9S12G Family Reference Manual, Rev.1.23
Section
29.4.5.
1036

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