S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 1151

• Manufacturer Part Number: S9S12GN16F0VLF
• Description: 16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN16F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 1024 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

31.3.2.6
The FERCNFG register enables the Flash error interrupts for the FERSTAT flags.
All assigned bits in the FERCNFG register are readable and writable.
Freescale Semiconductor
Offset Module Base + 0x0005
IGNSF
Reset
FDFD
FSFD
Field
CCIE
7
4
1
0
W
R
Command Complete Interrupt Enable — The CCIE bit controls interrupt generation when a Flash command
has completed.
0 Command complete interrupt disabled
1 An interrupt will be requested whenever the CCIF flag in the FSTAT register is set (see
Ignore Single Bit Fault — The IGNSF controls single bit fault reporting in the FERSTAT register (see
Section
0 All single bit faults detected during array reads are reported
1 Single bit faults detected during array reads are not reported and the single bit fault interrupt will not be
read operations and check the associated interrupt routine. The FDFD bit is cleared by writing a 0 to FDFD.
0 Flash array read operations will set the DFDIF flag in the FERSTAT register only if a double bit fault is detected
1 Any Flash array read operation will force the DFDIF flag in the FERSTAT register to be set (see
Force Single Bit Fault Detect
read operations and check the associated interrupt routine. The FSFD bit is cleared by writing a 0 to FSFD.
0 Flash array read operations will set the SFDIF flag in the FERSTAT register only if a single bit fault is detected
1 Flash array read operation will force the SFDIF flag in the FERSTAT register to be set (see
Force Double Bit Fault Detect — The FDFD bit allows the user to simulate a double bit fault during Flash array
Flash Error Configuration Register (FERCNFG)
0
0
7
generated
Section
register is set (see
and an interrupt will be generated as long as the SFDIE interrupt enable in the FERCNFG register is set (see
Section
31.3.2.8).
31.3.2.7) and an interrupt will be generated as long as the DFDIE interrupt enable in the FERCNFG
31.3.2.6)
Figure 31-10. Flash Error Configuration Register (FERCNFG)
= Unimplemented or Reserved
0
0
6
Section
MC9S12G Family Reference Manual, Rev.1.23
Table 31-13. FCNFG Field Descriptions
31.3.2.6)
0
0
5
—
The FSFD bit allows the user to simulate a single bit fault during Flash array
0
0
4
Description
0
0
3
240 KByte Flash Module (S12FTMRG240K2V1)
0
0
2
DFDIE
0
1
Section
Section
31.3.2.7)
SFDIE
31.3.2.7)
0
0
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