S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 372

Manufacturer Part Number

S9S12GN16F0VLF

16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM

Manufacturer

Freescale Semiconductor

Processor Series

Data Bus Width

Maximum Clock Frequency

Program Memory Size

Data Ram Size

Operating Supply Voltage

3.13 V to 5.5 V

Operating Temperature Range

- 40 C to + 85 C

Package / Case

Mounting Style

S12 Clock, Reset and Power Management Unit (S12CPMU)

The CPMUREFDIV register provides a ﬁner granularity for the PLL multiplier steps when using the

external oscillator as reference.

Read: Anytime

Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has

The REFFRQ[1:0] bits are used to conﬁgure the internal PLL ﬁlter for optimal stability and lock time. For

correct PLL operation the REFFRQ[1:0] bits have to be selected according to the actual REFCLK

frequency as shown in

If IRC1M is selected as REFCLK (OSCE=0) the PLL ﬁlter is ﬁxed conﬁgured for the 1MHz <= f

2MHz range. The bits can still be written but will have no effect on the PLL ﬁlter conﬁguration.

For OSCE=1, setting the REFFRQ[1:0] bits incorrectly can result in a non functional PLL (no locking

and/or insufﬁcient stability).

If XOSCLCP is enabled (OSCE=1)

If XOSCLCP is disabled (OSCE=0)

S12CPMU Reference Divider Register (CPMUREFDIV)

Write to this register clears the LOCK and UPOSC status bits.

Table 10-2. Reference Clock Frequency Selection if OSC_LCP is enabled

Figure 10-5. S12CPMU Reference Divider Register (CPMUREFDIV)

REFCLK Frequency Ranges

MC9S12G Family Reference Manual,

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Freescale Semiconductor