S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 272

• Manufacturer Part Number: S9S12GN16F0VLF
• Description: 16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN16F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 1024 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

S12G Memory Map Controller (S12GMMCV1)
The reset value of 0xE ensures that there is linear Flash space available between addresses 0x0000 and
0xFFFF out of reset.
The fixed 16KB page from 0xC000-0xFFFF is the page number 0xF.
5.4
The S12GMMC block performs several basic functions of the S12G sub-system operation: MCU
operation modes, priority control, address mapping, select signal generation and access limitations for the
system. Each aspect is described in the following subsections.
5.4.1
5.4.2
5.4.2.1
The BDM firmware lookup tables and BDM register memory locations share addresses with other
modules; however they are not visible in the memory map during user’s code execution. The BDM
memory resources are enabled only during the READ_BD and WRITE_BD access cycles to distinguish
between accesses to the BDM memory area and accesses to the other modules. (Refer to BDM Block
Guide for further details).
When the MCU enters active BDM mode, the BDM firmware lookup tables and the BDM registers
become visible in the local memory map in the range 0xFF00-0xFFFF (global address 0x3_FF00 -
0x3_FFFF) and the CPU begins execution of firmware commands or the BDM begins execution of
hardware commands. The resources which share memory space with the BDM module will not be visible
in the memory map during active BDM mode.
Please note that after the MCU enters active BDM mode the BDM firmware lookup tables and the BDM
registers will also be visible between addresses 0xBF00 and 0xBFFF if the PPAGE register contains value
of 0x0F.
5.4.2.1.1
Expansion of the CPU Local Address Map
The program page index register in S12GMMC allows accessing up to 256KB of address space in the
global memory map by using the four index bits (PPAGE[3:0]) to page 16x16 KB blocks into the program
page window located from address 0x8000 to address 0xBFFF in the local CPU memory map.
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Normal single chip mode
This is the operation mode for running application code. There is no external bus in this mode.
Special single chip mode
This mode is generally used for debugging operation, boot-strapping or security related operations.
The active background debug mode is in control of the CPU code execution and the BDM firmware
is waiting for serial commands sent through the BKGD pin.
Functional Description
MCU Operating Modes
Memory Map Scheme
CPU and BDM Memory Map Scheme
Expansion of the Local Address Map
MC9S12G Family Reference Manual,
Rev.1.23
Freescale Semiconductor