S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 643

• Manufacturer Part Number: S9S12GN16F0VLF
• Description: 16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
• Manufacturer: Freescale Semiconductor

Specifications of S9S12GN16F0VLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 1024 B
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Package / Case: TSSOP-20
• Mounting Style: SMD/SMT

Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see
0, 1, 4, 5, the selection is shown in
19.3.2.4
This register selects the prescale clock source for clocks A and B independently.
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x0003
PCLK[7:0]
Reset
Field
7-0
unavailable bits return a zero
W
R
Pulse Width Channel 7-0 Clock Select
0 Clock A or B is the clock source for PWM channel 7-0, as shown in
1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in
PWM Prescale Clock Select Register (PWMPRCLK)
0
0
7
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
PCLKAB[2,3,6,7]
PCLKAB[0,1,4,5]
Figure 19-6. PWM Prescale Clock Select Register (PWMPRCLK)
Section 19.3.2.7, “PWM Clock A/B Select Register
PCKB2
Table 19-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
Table 19-6. PWM Channel 2, 3, 6, 7 Clock Source Selection
= Unimplemented or Reserved
0
6
0
0
1
1
0
0
1
1
MC9S12G Family Reference Manual, Rev.1.23
Table 19-4. PWMCLK Field Descriptions
Table
PCKB1
0
5
PCLK[0,1,4,5]
PCLK[2,3,6,7]
19-5; For Channel 2, 3, 6, 7, the selection is shown in
0
1
0
1
0
1
0
1
PCKB0
NOTE
0
4
Description
Clock Source Selection
Clock Source Selection
0
0
3
Clock SA
Clock SB
Clock SB
Clock SA
Clock A
Clock B
Clock B
Clock A
Table 19-5
PCKA2
Pulse-Width Modulator (S12PWM8B8CV2)
Table 19-5
(PWMCLKAB)). For Channel
0
2
and
and
PCKA1
Table
0
Table
1
19-6.
19-6.
Table
PCKA0
0
0
19-6.
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