S9S12GN16F0VLF Freescale Semiconductor, S9S12GN16F0VLF Datasheet - Page 740

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S9S12GN16F0VLF

Manufacturer Part Number
S9S12GN16F0VLF
Description
16-bit Microcontrollers - MCU 16-bit16k Flash 2k RAM
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of S9S12GN16F0VLF

Rohs
yes
Core
S12
Processor Series
MC9S12G
Data Bus Width
16 bit
Maximum Clock Frequency
25 MHz
Program Memory Size
16 KB
Data Ram Size
1024 B
On-chip Adc
Yes
Operating Supply Voltage
3.13 V to 5.5 V
Operating Temperature Range
- 40 C to + 85 C
Package / Case
TSSOP-20
Mounting Style
SMD/SMT
Timer Module (TIM16B6CV3)
22.3.2.8
Read: Anytime
Write: Anytime.
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero
22.3.2.9
Read: Anytime
Write: Anytime.
742
Module Base + 0x000C
Module Base + 0x000D
C5I:C0I
Reset
Reset
Field
5:0
W
W
R
R
RESERVED RESERVED
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
TOI
Timer Interrupt Enable Register (TIE)
Timer System Control Register 2 (TSCR2)
0
0
7
7
= Unimplemented or Reserved
Figure 22-15. Timer System Control Register 2 (TSCR2)
0
0
0
6
6
EDGnB
Figure 22-14. Timer Interrupt Enable Register (TIE)
Table 22-9. Edge Detector Circuit Configuration
1
MC9S12G Family Reference Manual,
Table 22-10. TIE Field Descriptions
C5I
EDGnA
0
0
0
5
5
1
Capture on any edge (rising or falling)
C4I
0
0
0
4
4
Description
Configuration
RESERVED
C3I
0
0
3
3
Rev.1.23
PR2
C2I
0
0
2
2
Freescale Semiconductor
PR1
C1I
0
0
1
1
PR0
C0I
0
0
0
0

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