S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 1223

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

A.7
A.7.1
The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV
register. The frequency of this derived clock must be set within the limits specified as f
module does not have any means to monitor the frequency and will not prevent program or erase operation
at frequencies above or below the specified minimum. When attempting to program or erase the NVM
module at a lower frequency, a full program or erase transition is not assured.
The following sections provide equations which can be used to determine the time required to execute
specific flash commands. All timing parameters are a function of the bus clock frequency, f
program and erase times are also a function of the NVM operating frequency, f
timing parameters can be found in
Freescale Semiconductor
1
2
Characteristics noted under conditions 3.13V <= VDDA <= 5.5V>, -40˚C < Tj < 150˚C >, VRH=VDDA, VRL=VSSA
unless otherwise noted. Typical values noted reflect the approximate parameter mean at T
conditions unless otherwise noted.
Num
DRIVE bit = 1 is not recommended in this case.
DRIVE bit = 0 is not allowed with this high load.
10
11
12
13
14
8
9
NVM
C
C
P
P
D
P
P
D
Timing Parameters
Output Voltage
unbuffered range A or B (load >= 50MΩ)
Output Voltage (DRIVE bit = 0)
buffered range A (load >= 100KΩ to VSSA)
buffered range A (load >= 100KΩ to VDDA)
buffered range B (load >= 100KΩ to VSSA)
buffered range B (load >= 100KΩ to VDDA)
Output Voltage (DRIVE bit = 1)
buffered range B with 6.4KΩ load into resistor
divider of 800Ω /6.56KΩ between VDDA and
VSSA.
(equivalent load is >= 65KΩ to VSSA) or
(equivalent load is >= 7.5KΩ to VDDA)
Buffer Output Capacitive load
Buffer Output Offset
Settling time
Reverence voltage high
Table A-33. Static Electrical Characteristics - DAC_8B5V
Ratings
MC9S12G Family Reference Manual, Rev.1.23
Table
1
2
A-34.
Symbol
V
C
t
V
V
V
V
delay
offset
load
refh
out
out
out
VDDA-0.1V
0.15
Min
-30
0
0
-
full DAC Range A or B
full DAC Range B
full DAC Range B
VDDA
Typ
NVMOP
A
3
-
-
-
-
= 25˚C under nominal
VDDA+0.1V
VDDA-0.15
. A summary of key
Electrical Characteristics
NVMOP
VDDA
Max
100
+30
5
NVMBUS
. The NVM
Unit
mV
pF
µs
V
V
V
V
. All
1225