S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 624

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

Freescale’s Scalable Controller Area Network (S12MSCANV3)
18.4.3.1
The MSCAN protects the user from accidentally violating the CAN protocol through programming errors.
The protection logic implements the following features:
18.4.3.2
Figure 18-43
The clock source bit (CLKSRC) in the CANCTL1 register (18.3.2.2/18-592) defines whether the internal
CANCLK is connected to the output of a crystal oscillator (oscillator clock) or to the bus clock.
The clock source has to be chosen such that the tight oscillator tolerance requirements (up to 0.4%) of the
CAN protocol are met. Additionally, for high CAN bus rates (1 Mbps), a 45% to 55% duty cycle of the
clock is required.
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the
bus clock due to jitter considerations, especially at the faster CAN bus rates.
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The receive and transmit error counters cannot be written or otherwise manipulated.
All registers which control the configuration of the MSCAN cannot be modified while the MSCAN
is on-line. The MSCAN has to be in Initialization Mode. The corresponding INITRQ/INITAK
handshake bits in the CANCTL0/CANCTL1 registers (see
Register 0
— MSCAN control 1 register (CANCTL1)
— MSCAN bus timing registers 0 and 1 (CANBTR0, CANBTR1)
— MSCAN identifier acceptance control register (CANIDAC)
— MSCAN identifier acceptance registers (CANIDAR0–CANIDAR7)
— MSCAN identifier mask registers (CANIDMR0–CANIDMR7)
The TXCAN is immediately forced to a recessive state when the MSCAN goes into the power
down mode or initialization mode (see
Section 18.4.4.5, “MSCAN Initialization
The MSCAN enable bit (CANE) is writable only once in normal system operation modes, which
provides further protection against inadvertently disabling the MSCAN.
Oscillator Clock
Bus Clock
Protocol Violation Protection
Clock System
shows the structure of the MSCAN clock generation circuitry.
(CANCTL0)”) serve as a lock to protect the following registers:
MC9S12G Family Reference Manual,
Figure 18-43. MSCAN Clocking Scheme
CLKSRC
Section 18.4.5.6, “MSCAN Power Down
Mode”).
CANCLK
MSCAN
CLKSRC
Prescaler
Rev.1.23
(1 .. 64)
Section 18.3.2.1, “MSCAN Control
Time quanta clock (Tq)
Freescale Semiconductor
Mode,” and