S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 175

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

2.3.9
2.3.10
Freescale Semiconductor
PM3
PM2
PM1
PM0
PP7-PP6
PP5-PP4
Pins PM3-0
Pins PP7-0
• 64/100 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2
• Signal priority:
• 64/100 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. If the SCI2
• Signal priority:
• Except 20 TSSOP: The TXCAN signal is mapped to this pin when used with the CAN function. The
• 32 LQFP: The SCI1 TXD signal is mapped to this pin when used with the SCI function. If the SCI1 TXD
• 48 LQFP: The SCI2 TXD signal is mapped to this pin when used with the SCI function. If the SCI2 TXD
• Signal priority:
• Except 20 TSSOP: The RXCAN signal is mapped to this pin when used with the CAN function. The
• 32 LQFP: The SCI1 RXD signal is mapped to this pin when used with the SCI function. The enabled
• 48 LQFP: The SCI2 RXD signal is mapped to this pin when used with the SCI function. The enabled
• Signal priority:
• 64/100 LQFP: The PWM channels 7 and 6 signal are mapped to these pins when used with the PWM
• 64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
• 48/64/100 LQFP: The PWM channels 5 and 4 signal are mapped to these pins when used with the
• 48/64/100 LQFP: Pin interrupts can be generated if enabled in input or output mode.
• Signal priority:
TXD signal is enabled the I/O state will depend on the SCI2 configuration.
64/100 LQFP: TXD2 > GPO
RXD signal is enabled the I/O state will be forced to be input.
64/100 LQFP: RXD2 > GPO
enabled CAN forces the I/O state to be an output.
signal is enabled the I/O state will depend on the SCI1 configuration.
signal is enabled the I/O state will depend on the SCI2 configuration.
32 LQFP: TXCAN > TXD1 > GPO
48 LQFP: TXCAN > TXD2 > GPO
64/100 LQFP: TXCAN > GPO
enabled CAN forces the I/O state to be an input. If CAN is active the selection of a pulldown device on
the RXCAN input has no effect.
SCI1 RXD signal forces the I/O state to an input.
SCI2 RXD signal forces the I/O state to an input.
32 LQFP: RXCAN > RXD1 > GPO
48 LQFP: RXCAN > RXD2 > GPO
64/100 LQFP: RXCAN > GPO
function. The enabled PWM channel forces the I/O state to be an output.
64/100 LQFP: PWM > GPO
PWM function. The enabled PWM channel forces the I/O state to be an output.
48/64/100 LQFP: PWM > GPO
MC9S12G Family Reference Manual, Rev.1.23
Table 2-13. Port
Table 2-14. Port
M
P
Pins PM3-0
Pins PP7-0
Port Integration Module (S12GPIMV1)
177