S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 305

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

Since the host knows the target serial clock frequency, the SYNC command (used to abort a command)
does not need to consider the lower possible target frequency. In this case, the host could issue a SYNC
very close to the 128 serial clock cycles length. Providing a small overhead on the pulse length in order to
assure the SYNC pulse will not be misinterpreted by the target. See
Timed Reference
Figure 7-12
command. Note that, after the command is aborted a new command could be issued by the host computer.
Figure 7-13
occur if a POD device is connected to the target BKGD pin and the target is already in debug active mode.
Consider that the target CPU is executing a pending BDM command at the exact moment the POD is being
connected to the BKGD pin. In this case, an ACK pulse is issued along with the SYNC command. In this
case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse. Since this is not
a probable situation, the protocol does not prevent this conflict from happening.
Freescale Semiconductor
(Target MCU)
Drives SYNC
To BKGD Pin
BKGD Pin
Target MCU
BDM Clock
BKGD Pin
BKGD Pin
Drives to
Host
shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE
shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could
READ_BYTE
Figure 7-12
Pulse”.
the READ_BYTE Command
READ_BYTE CMD is Aborted
Host
Figure 7-12. ACK Abort Procedure at the Command Level
and Starts to Execute
Figure 7-13. ACK Pulse and SYNC Request Conflict
does not represent the signals in a true timing scale
by the SYNC Request
Memory Address
Target
Host SYNC Request Pulse
BDM Decode
MC9S12G Family Reference Manual, Rev.1.23
(Out of Scale)
ACK Pulse
16 Cycles
Host and
Target Drive
to BKGD Pin
At Least 128 Cycles
NOTE
Electrical Conflict
High-Impedance
READ_STATUS
Host
SYNC Response
From the Target
(Out of Scale)
Target
New BDM Command
Section 7.4.9, “SYNC — Request
Background Debug Module (S12SBDMV1)
New BDM Command
Host
Speedup Pulse
Target
307