S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 171

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

2.3.5
2.3.6
2.3.7
Freescale Semiconductor
PD7-PD0
PE1
PE0
PT7-PT6
PT5
Pins PD7-0
Pins PE1-0
Pins PT7-0
• These pins feature general-purpose I/O functionality only.
• If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is disabled.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. The TIM
• 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The
• 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The
• Signal priority:
• If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. The TIM
• 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The
• 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The
• Signal priority:
• 64/100 LQFP: The TIM channels 7 and 6 signal are mapped to these pins when used with the timer
• Signal priority:
• 48/64/100 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function.
• Signal priority:
TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
forces the I/O state to be an output for a timer port associated with an enabled output compare.
enabled PWM channel forces the I/O state to be an output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: XTAL > TXD0 > IOC3 > PWM1 > GPO
Others: XTAL > GPO
disabled.
RXD signal is enabled and routed here the I/O state will be forced to input.
forces the I/O state to be an output for a timer port associated with an enabled output compare.
enabled PWM channel forces the I/O state to be an output.
enabled external trigger function has no effect on the I/O state. Refer to
Triggers
20 TSSOP: EXTAL > RXD0 > IOC2 > PWM0 > GPO
Others: EXTAL > GPO
function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
64/100 LQFP: IOC7-6 > GPO
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can
still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires
the timer input capture function to be enabled.
48/64/100 LQFP: IOC5 > GPO
ETRIG3-0”.
ETRIG3-0”.
MC9S12G Family Reference Manual, Rev.1.23
Table 2-10. Port
Table 2-11. Port
Table 2-9. Port
D
E
T
Pins PD7-0
Pins PE1-0
Pins PT7-0
Port Integration Module (S12GPIMV1)
Section 2.6.4, “ADC External
Section 2.6.4, “ADC External
173