S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 1247

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

Appendix B
Detailed Register Address Map
Revision History
B.1
The following tables show the detailed register map of the MC9S12G-Family.
0x0000–0x0009 Port Integration Module (PIM) Map 1 of 6
Freescale Semiconductor
Address
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
0x0008
0x0009
Rev 0.05
Rev 0.06
Rev 0.07
Rev 0.08
Rev 0.09
Number
Version
Detailed Register Map
PORTC
PORTD
PORTB
PORTE
PORTA
DDRA
DDRB
DDRC
DDRD
DDRE
Name
30-Aug-2010
18-Oct-2010
24-Apr-2012
9-Nov-2010
4-Dec-2010
This is a summary of all register bits implemented on MC9S12G devices.
Each member of the MC9S12G-Family implements the subset of registers,
which is associated with its feature set (see
Revision
Date
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
DDRA7
DDRB7
DDRC7
DDRD7
Bit 7
PC7
PD7
PA7
PB7
0
0
• Updated ADCCTL2 register in
• Updated CPMUOSC register in
• Updated ADC registers in
• Updated CPMU registers in
• Updated PIM registers in
• Typos and formatting
MC9S12G Family Reference Manual, Rev.1.23
DDRA6
DDRB6
DDRC6
DDRD6
Bit 6
PB6
PC6
PD6
PA6
0
0
DDRA5
DDRB5
DDRC5
DDRD5
Bit 5
PB5
PC5
PD5
PA5
0
0
NOTE
Appendix B, “Detailed Register Address
Appendix B, “Detailed Register Address
Appendix B, “Detailed Register Address
Description of Changes
DDRC4
DDRD4
Appendix B, “Detailed Register Address
DDRA4
DDRB4
Appendix B, “Detailed Register Address
Bit 4
PB4
PC4
PD4
PA4
Table
0
0
1-1).
DDRC3
DDRD3
DDRA3
DDRB3
Bit 3
PB3
PC3
PD3
PA3
0
0
DDRC2
DDRD2
DDRA2
DDRB2
Bit 2
PB2
PC2
PD2
PA2
0
0
Detailed Register Address Map
Map”.
Map”.
DDRA1
DDRB1
DDRC1
DDRD1
DDRE1
Map”.
Bit 1
PC1
PD1
PB1
PE1
PA1
Map”.
Map”.
DDRC0
DDRD0
DDRE0
DDRA0
DDRB0
Bit 0
PA 0
PC0
PD0
PB0
PE0
1249