S9S12G64F1MLC Freescale Semiconductor, S9S12G64F1MLC Datasheet - Page 341

• Manufacturer Part Number: S9S12G64F1MLC
• Description: 16-bit Microcontrollers - MCU S12CORE,64K FLASH,AU
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F1MLC

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 4 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-32
• Mounting Style: SMD/SMT

8.4.5.3.1
The format of the bits is dependent upon the active trace mode as described below.
Field2 Bits in Detail Mode
In Detail Mode the CSZ and CRW bits indicate the type of access being made by the CPU.
Field2 Bits in Normal and Loop1 Modes
Freescale Semiconductor
ADDR[17]
ADDR[16]
PC17
CRW
CSD
CSZ
CVA
Bit
Bit
3
2
1
0
3
2
1
Access Type Indicator— This bit indicates if the access was a byte or word size when tracing in Detail Mode
0 Word Access
1 Byte Access
Read Write Indicator — This bit indicates if the corresponding stored address corresponds to a read or write
access when tracing in Detail Mode.
0 Write Access
1 Read Access
Address Bus bit 17— Corresponds to system address bus bit 17.
Address Bus bit 16— Corresponds to system address bus bit 16.
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored
address is a source or destination address. This bit has no meaning in Compressed Pure PC mode.
0 Source Address
1 Destination Address
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector
address. Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set.
This bit has no meaning in Compressed Pure PC mode.
0 Non-Vector Destination Address
1 Vector Destination Address
Program Counter bit 17— In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Information Bit Organization
MC9S12G Family Reference Manual, Rev.1.23
Figure 8-25. Field2 Bits in Detail Mode
Table 8-39. PCH Field Descriptions
Figure 8-26. Information Bits PCH
CSD
Bit 3
CSZ
Bit 3
Table 8-38. Field Descriptions
CRW
Bit 2
Bit 2
CVA
ADDR[17] ADDR[16]
Description
Description
PC17
Bit 1
Bit 1
PC16
Bit 0
Bit 0
S12S Debug Module (S12SDBGV2)
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