5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 11

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

AV-51001
2013.01.11
Arria V Device Overview
Maximum Resources
Package Plan
14
15
16
Table 10: Maximum Resource Counts for Arria V SX Devices Preliminary
Table 11: Package Plan for Arria V SX Devices Preliminary
Logic Elements (LE) (K)
ALM
Register
Memory (Kb)
Variable-precision DSP Block
18 x 18 Multiplier
FPGA PLL
HPS PLL
6 Gbps Transceiver
FPGA GPIO
HPS I/O
LVDS
PCIe Hard IP Block
FPGA Hard Memory Controller
HPS Hard Memory Controller
ARM Cortex-A9 MPCore Processor
The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs.
The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os
includes transceiver I/Os.
For the number of LVDS channels in each package, refer to the
in Arria V Devices
Member
Code
B3
B5
16
14
15
FPGA
GPIO
250
250
chapter.
Resource
(31 mm)
HPS I/O
F896
210
210
Transmitter
XCVR
Receiver
12
12
MLAB
M10K
FPGA
GPIO
385
385
(35 mm)
HPS I/O
F1152
210
210
High-Speed Differential I/O Interfaces and DPA
Dual-core
132,075
528,300
17,290
2,014
1,618
350
809
528
216
120
136
B3
10
30
3
2
3
1
XCVR
18
18
Member Code
Arria V Device Overview
FPGA
GPIO
540
540
(40 mm)
HPS I/O
F1517
Dual-core
210
210
174,340
697,360
22,820
2,658
1,068
2,136
Altera Corporation
462
528
216
120
136
B5
14
30
3
2
3
1
XCVR
30
30
11