5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 30

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
30
Hardware and Software Development
Dynamic and Partial Reconfiguration
Dynamic Reconfiguration
Partial Reconfiguration
For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to
the HPS interfaces using the Qsys system integration tool in the Quartus II software.
For software development, the ARM-based SoC FPGA devices inherit the rich software development
ecosystem available for the ARM Cortex-A9 MPCore processor. The software development process for
Altera SoC FPGAs follows the same steps as those for other SoC devices from other manufacturers. Support
for Linux, VxWorks
on the operating systems support availability, contact the
You can begin device-specific firmware and software development on the Altera SoC FPGA Virtual Target.
The Virtual Target is a fast PC-based functional simulation of a target development system—a model of a
complete development board that runs on a PC. The Virtual Target enables the development of device-specific
production software that can run unmodified on actual hardware.
The Arria V devices support dynamic reconfiguration and partial reconfiguration.
The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA
settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal
for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA,
PCS, and PCIe hard IP blocks with dynamic reconfiguration.
Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain
operational. This capability is important in systems with critical uptime requirements because it allows you
to make updates or adjust functionality without disrupting services.
Apart from lowering cost and power consumption, partial reconfiguration increases the effective logic density
of the device because placing device functions that do not operate simultaneously is not necessary. Instead,
you can store these functions in external memory and load them whenever the functions are required. This
capability reduces the size of the device because it allows multiple applications on a single device—saving
the board space and reducing the power consumption.
Altera simplifies the time-intensive task of partial reconfiguration by building this capability on top of the
proven incremental compile and design flow in the Quartus II design software. With the Altera
you do not need to know all the intricate device architecture details to perform a partial reconfiguration.
Partial reconfiguration is supported through the FPP x16 configuration interface. You can seamlessly use
partial reconfiguration in tandem with dynamic reconfiguration to enable simultaneous partial reconfiguration
of both the device core and transceivers.
Arria V Device Overview
®
, and other operating systems will be available for the SoC FPGAs. For more information
Altera sales
team.
Arria V Device Overview
®
solution,
2013.01.11
AV-51001