5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 28

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
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SoC FPGA with HPS
HPS Features
System Peripherals and Debug Access Port
Figure 12: HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Each SoC FPGA combines an FPGA fabric and an HPS in a single device. This combination delivers the
flexibility of programmable logic with the power and cost savings of hard IP in these ways:
The HPS consists of a dual-core ARM MPCore processor, a rich set of peripherals, and a shared multiport
SDRAM memory controller, as shown in the following figure.
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated
DMA controller. For modules without an integrated DMA controller, an additional DMA controller module
provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are
multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
Arria V Device Overview
Reduces board space, system power, and bill of materials cost by eliminating a discrete embedded processor
Allows you to differentiate the end product in both hardware and software, and to support virtually any
interface standard
Extends the product life and revenue through in-field hardware and software updates
(UART, Timer, I
NAND Flash
Configuration
Access Port
Controller
MAC (2x)
Controller
Controller
SD/MMC
OTG (2x)
Controller
Ethernet
(Trace)
Debug
DMA
USB
ETR
2
FPGA-to-HPS
Manager
C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and
FPGA
Interconnect
Level 3
HPS-to-FPGA
Quad SPI Flash Controller)
Memory Management Unit
HPS-to-FPGA
32 KB Instruction Cache,
ACP
STM
32 KB Data Cache, and
Lightweight
with NEON/FPU,
ARM Cortex-A9
Peripherals
CPU0
ARM Cortex-A9 MPCore
Level 2 Cache (512 KB)
MPU Subsystem
On-Chip RAM
Boot ROM
64 KB
64 KB
SCU
FPGA Fabric
Memory Management Unit
32 KB Instruction Cache,
32 KB Data Cache, and
HPS
with NEON/FPU,
ARM Cortex-A9
CPU1
FPGA-to-HPS SDRAM
DDR SDRAM
Optional ECC
Controller
Multiport
with
Arria V Device Overview
2013.01.11
AV-51001