5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 32

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
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Document Revision History
January 2013
November 2012
October 2012
July 2012
June 2012
Additionally, Arria V devices contain several hard IP blocks, including PCIe Gen1, Gen2, and Gen3, GbE,
SRIO, GPON, and CPRI protocols, that reduce logic resources and deliver substantial power savings of up
to 25% less power than equivalent soft implementations.
Arria V Device Overview
Date
2013.01.11
2012.11.19
Version
3.0
2.1
2.0
Added the L optional suffix to the Arria V GZ ordering code for the
-I3 speed grade.
Added a note about the power-up sequence requirement if you plan
to migrate your design from the Arria V GX A5 and A7, and Arria V
GT C7 devices to other Arria V devices.
Updated the summary of features.
Updated Arria V GZ information regarding 3.3 V I/O support.
Removed Arria V GZ engineering sample ordering code.
Updated the maximum resource counts for Arria V GX and GZ.
Updated Arria V ST ordering codes for transceiver count.
Updated transceiver counts for Arria V ST packages.
Added simplified floorplan diagrams for Arria V GZ, SX, and ST.
Added FPP x32 configuration mode for Arria V GZ only.
Updated CvP (PCIe) remote system update support information.
Added HPS external memory performance information.
Updated template.
Added Arria V GZ information.
Updated Table 1, Table 2, Table 3, Table 14, Table 15, Table 16, Table
17, Table 18, Table 19, Table 20, and Table 21.
Added the “Arria V GZ” section.
Added Table 8, Table 9 and Table 22.
Added –I3 speed grade to Figure 1 for Arria V GX devices.
Updated the 6-Gbps transceiver speed from 6.553 Gbps to 6.5536 Gbps
in Figure 3 and Figure 1.
Restructured the document.
Added the “Embedded Memory Capacity” and “Embedded Memory
Configurations” sections.
Added Table 1, Table 3, Table 12, Table 15, and Table 16.
Updated Table 2, Table 4, Table 5, Table 6, Table 7, Table 8, Table 9,
Table 10, Table 11, Table 13, Table 14, and Table 19.
Updated Figure 1, Figure 2, Figure 3, Figure 4, and Figure 8.
Updated the “FPGA Configuration and Processor Booting” and
“Hardware and Software Development” sections.
Text edits throughout the document.
Changes
Arria V Device Overview
2013.01.11
AV-51001