5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 14

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
14
I/O Vertical Migration for Arria V Devices
Adaptive Logic Module
Figure 6: Vertical Migration Capability Across Arria V Device Packages and Densities Preliminary
The arrows indicate the vertical migration paths. Some packages have several migration paths. The devices
included in each vertical migration path are shaded. You can also migrate your design across device densities
in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.
You can achieve the vertical migration shaded in red if you use only up to 320 GPIOs, up to nine 6 Gbps
transceiver channels, and up to four 10 Gbps transceiver (for Arria V GT devices). This migration path is
not shown in the Quartus II software Pin Migration View.
Note:
Note:
Arria V devices use a 28 nm ALM as the basic building block of the logic fabric.
The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT) with four dedicated
registers to help improve timing closure in register-rich designs and achieve an even higher design packing
capability than previous generations.
Arria V Device Overview
To verify the pin migration compatibility, use the Pin Migration View window in the Quartus
software Pin Planner. For more information, refer to the
Quartus II Handbook.
If you plan to migrate your design from the Arria V GX A5 and A7, and Arria V GT C7 devices to
other Arria V devices, adhere to the power-up sequence described in the
V Devices
Arria V GX
Arria V GZ
Arria V GT
Arria V SX
Arria V ST
Variant
chapter.
Member
Code
C3
C7
D3
D7
D3
D5
A1
A3
A5
A7
B1
B3
B5
B7
E1
E3
E5
E7
B3
B5
F672
F780
Package
F896
I/O Management”
F1152
Power Management in Arria
Arria V Device Overview
chapter in the
F1517
2013.01.11
AV-51001
®
II