5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 19

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

AV-51001
2013.01.11
Arria V Device Overview
FPGA General Purpose I/O
PCIe Gen1, Gen2, and Gen 3 Hard IP
PLL Features
Fractional PLL
The PLLs in the Arria V devices support the following features:
In addition to integer PLLs, the Arria V devices use a fractional PLL architecture. The devices have up to 16
PLLs, each with 18 output counters. One fractional PLL can use up to 18 output counters and two adjacent
fractional PLLs share the 18 output counters. You can use the output counters to reduce PLL usage in two
ways:
If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency
synthesis—removing the need for off-chip reference clock sources in your design.
The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose
fractional PLLs by the FPGA fabric.
Arria V devices offer highly configurable GPIOs. The following list describes the features of the GPIOs:
Arria V devices contain PCIe hard IP that is designed for performance, ease-of-use, and increased
functionality. The PCIe hard IP consists of the MAC, data link, and transaction layers.
Frequency synthesis
On-chip clock deskew
Jitter attenuation
Counter reconfiguration
Programmable output clock duty cycles
PLL cascading
Reference clock switchover
Programmable bandwidth
Dynamic phase shift
Zero delay buffers
Reduce the number of oscillators that are required on your board by using fractional PLLs
Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies
from a single reference clock source
Programmable bus hold and weak pull-up
LVDS output buffer with programmable differential output voltage (V
pre-emphasis
On-chip parallel termination (R
impedance variation
On-chip dynamic termination that has the ability to swap between series and parallel termination,
depending on whether there is read or write on a common bus for signal integrity
Unused voltage reference ( VREF ) pins that can be configured as user I/Os (Arria V GX, GT, SX, and
ST only)
Easy timing closure support using the hard read FIFO in the input register path, and delay-locked loop
(DLL) delay chain with fine and coarse architecture
T
OCT) for all I/O banks with OCT calibration to limit the termination
Arria V Device Overview
OD
) and programmable
Altera Corporation
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