5AGXBA1D4F31C4N Altera Corporation, 5AGXBA1D4F31C4N Datasheet - Page 20

• Manufacturer Part Number: 5AGXBA1D4F31C4N
• Description: FPGA - Field Programmable Gate Array FPGA - Arria V GX 2830 LABS 416 IOs
• Manufacturer: Altera Corporation
• Series: Arria V GXr

Specifications of 5AGXBA1D4F31C4N

• Rohs: yes
• Number Of Logic Blocks: 2830
• Number Of I/os: 416
• Maximum Operating Frequency: 800 MHz
• Operating Supply Voltage: 1.2 V to 1.8 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: FBGA-896
• Distributed Ram: 8463 kbit
• Minimum Operating Temperature: 0 C

Altera Corporation
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External Memory Interface
Hard and Soft Memory Controllers
External Memory Performance
Figure 8: PCIe Multifunction for Arria V Devices
Table 18: External Memory Interface Performance in Arria V Devices
DDR3 SDRAM
DDR2 SDRAM
The PCIe hard IP supports PCIe Gen3, Gen 2, and Gen 1 end point and root port for up to x8 lane
configuration.
The PCIe endpoint support includes multifunction support for up to eight functions, as shown in the
following figure. The integrated multifunction support reduces the FPGA logic requirements by up to
20,000 LEs for PCIe designs that require multiple peripherals.
The Arria V PCIe hard IP operates independently from the core logic. This independent operation allows
the PCIe link to wake up and complete link training in less than 100 ms while the Arria V device completes
loading the programming file for the rest of the device.
In addition, the PCIe hard IP in the Arria V device provides improved end-to-end datapath protection using
ECC.
This section provides an overview of the external memory interface in Arria V devices.
Arria V GX,GT, SX, and ST devices support up to four hard memory controllers for DDR3 and DDR2
SDRAM devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with
two chip selects and optional ECC. For the Arria V SoC FPGA devices, an additional hard memory controller
in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices.
All Arria V devices support soft memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices, QDR
II+, QDR II, and DDR II+ SRAM devices, and RLDRAM II devices for maximum flexibility.
Note:
Arria V Device Overview
Interface
DDR3 SDRAM leveling is supported only in Arria V GZ devices.
External System
Peripheral 1
Voltage (V)
Local
1.35
1.5
1.8
Host CPU
Complex
Root
Peripheral 2
Local
Arria V GX, GT, SX, and
Hard Controller (MHz)
PCIe Link
533
533
400
ST
FPGA Device
Arria V GX, GT, SX, and
667
667
400
ST
Soft Controller (MHz)
Arria V Device Overview
Arria V GZ
800
800
400
2013.01.11
AV-51001